ASM811, ASM812

6 of 10

Notice: The information in this document is subject to change without notice

4 Pin µP Voltage Supervisor with Manual Reset

October 2003

rev 1.0

MR Glitch Immunity

Note 3

100

ns

MR to RESET Propogation

Delay

Note 2

0.5

µs

MR Input Threshold

ASM811/812L/M/J

2.3

V

0.8

MR Input Threshold

ASM811/812R/S/T

V

MR Pullup Resistance

10

20

30

k

Ω

Low RESET Output Voltage

(ASM811)

ASM811R/S/T

0.3

0.4

0.3

V

ASM811L/M/J

High RESET Output Voltage

(ASM811)

ASM811R/S/T

V

ASM811L/M/J

Low RESET Output Voltage

(ASM812)

ASM812R/S/T

0.3

0.4

V

ASM812L/M/J

High RESET Output Voltage

(ASM812)

V

Active Reset Timeout Period

140

240

msec

Manual Active Reset Time-

out Period

MR returns HIGH

180

msec

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Notes:

1. Production testing done at TA = 25°C. Over-temperature specifications guaranteed by design only using six sigma design limits.

2. RESET output is active LOW for the ASM811 and RESET output is active HIGH for the ASM812.

3. Glitches of 100ns or less typically will not generate a reset pulse.