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SLG46121 数据表(PDF) 21 Page - Dialog Semiconductor |
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SLG46121 数据表(HTML) 21 Page - Dialog Semiconductor |
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21 / 98 page ![]() 000-0046121--106 Page 20 of 97 SLG46121 7.4 I/O Register Settings 7.4.1 PIN 2 Register Settings 7.4.2 PIN 3 Register Settings Table 6. PIN 2 Register Settings Signal Function Register Bit Address Register Definition PIN 2 Mode Control reg <624:623> 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved PIN 2 Pull Down Resistor Value Selection reg <626:625> 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor Table 7. PIN 3 Register Settings Signal Function Register Bit Address Register Definition PIN 3 Mode Control reg <629:627> 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain NMOS PIN 3 Pull Up/Down Resistor Value Selection reg <631:630> 00: Floating 01: 10 k Resistor 10: 100 k Resistor 11: 1 M Resistor PIN 3 Pull Up/Down Resistor Selection reg <632> 0: Pull Down Resistor 1: Pull Up Resistor PIN3 Driver Strength Selection reg <633> 0: 1X 1: 2X |
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