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SLG46170 数据表(PDF) 13 Page - Dialog Semiconductor |
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SLG46170 数据表(HTML) 13 Page - Dialog Semiconductor |
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13 / 87 page ![]() 000-0046170-103 Page 12 of 86 SLG46170 frequency settling time 2MHz auto 14 14 14 s variable (CLK period) 25kHz forced 0-40 0-40 0-40 s variable (CLK period) 2MHz forced 0-0.5 0-0.5 0-0.5 s tpd (non-delayed edge) 25kHz/2MHz either 35 14 10 ns Table 3. Typical Counter/Delay Offset Measurements. Parameter RC OSC Freq RC OSC Power VDD = 1.8 V VDD = 3.3V VDD = 5.0V Unit |
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