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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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HT48RA0 数据表(PDF) 3 Page - Holtek Semiconductor Inc |
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HT48RA0 数据表(HTML) 3 Page - Holtek Semiconductor Inc |
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3 / 32 page  D.C. Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VDD Operating Voltage ¾¾ 2.0 ¾ 3.6 V IDD Operating Current 3V No load, fSYS=4MHz ¾ 0.7 1.5 mA ISTB Standby Current 3V No load, system HALT ¾¾ 1 mA VIL1 Input Low Voltage for I/O Ports 3V ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O Ports 3V ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES)3V ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES)3V ¾ 0.9VDD ¾ VDD V VLVR Low Voltage Reset Voltage ¾¾ ¾ 1.9 2.0 V IOL I/O Ports Sink Current 3V VOL=0.1VDD 48 ¾ mA IOH PC0/REM Output Source Current 3V VOH=0.9VDD -2 -4 ¾ mA RPH Pull-high Resistance 3V ¾ 20 60 100 k W A.C. Characteristics Ta=25 °C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS System Clock 3V ¾ 400 ¾ 4000 kHz tRES External Reset Low Pulse Width ¾¾ 1 ¾¾ ms tSST System Start-up Timer Period ¾ Power-up, reset or wake-up from HALT ¾ 1024 ¾ tSYS tLVR Low Voltage Width to Reset ¾¾ 1 ¾¾ ms Note: tSYS=1/fSYS HT48RA0-2/HT48CA0-2 Rev. 1.50 3 July 23, 2004 Functional Description Execution Flow The HT48RA0-2/HT48CA0-2 system clock can be de- rived from a crystal/ceramic resonator oscillator. It is in- ternally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de- coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute within one cycle. If an instruc- tion changes the program counter, two cycles are required to complete the instruction. T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 T 1 T 2 T 3 T 4 F e t c h I N S T ( P C ) E x e c u t e I N S T ( P C - 1 ) F e t c h I N S T ( P C + 1 ) E x e c u t e I N S T ( P C ) F e t c h I N S T ( P C + 2 ) E x e c u t e I N S T ( P C + 1 ) P C P C + 1 P C + 2 S y s t e m C l o c k I n s t r u c t i o n C y c l e P C Execution Flow |
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