ADATE209

Rev. A | Page 12 of 16

0

0.2

0.4

0.6

0.8

1.0

–0.2

1.2

TIME (ns)

Figure 15. VHx = 2.0 V, VTx = 1.0 V, VLx = 0.0 V,

Transitions Between VHx/VLx and VTx

PULSE WIDTH (ns)

0.1

1

10

–30

–20

–10

0

10

20

30

NEGATIVE PULSE

POSITIVE PULSE

Figure 16. 1 V Minimum Pulse Width (VHx = 1.0 V, VLx = 0.0 V), CLC Disabled

PULSE WIDTH (ns)

0.1

1

10

–30

–20

–10

0

10

20

30

NEGATIVE PULSE

POSITIVE PULSE

Figure 17. 2 V Minimum Pulse Width (VHx = 2.0 V, VLx = 0.0 V), CLC Disabled

PULSE WIDTH (ns)

0.1

1

10

–30

–20

–10

0

10

20

30

NEGATIVE PULSE

POSITIVE PULSE

Figure 18. 3 V Minimum Pulse Width (VHx = 3.0 V, VLx = 0.0 V), CLC Disabled

VHx (V)

–25

–20

–15

–10

–5

0

5

–2

–1

0

1

2

3

4

50°C

70°C

90°C

Figure 19. Driver Linearity (VHx), VLx = −1.1 V, VTx = 1.0 V

–3

–2

–1

0

1

2

3

4

VLx (V)

–2

–1

0

1

2

3

4

50°C

70°C

90°C

Figure 20. Driver Linearity (VLx), VHx = 3.6 V, VTx = 1.0 V