5

ICS93V855

0497B—06/01/04

Switching Characteristics

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Max clock frequency

3

33

233

MHz

Application Frequency

Range

3

60

170

MHz

Input clock duty cycle

40

60

%

Input clock slew rate

12

v/ns

CLK stabilization

100

µs

Low-to high level propagation

delay time

1

CLK_IN to any output

5.5

ns

High-to low level propagation

delay time

1

CLK_IN to any output

5.5

ns

Output enable time

PD# to any output

5

ns

Output disable time

PD# to any output

5

ns

Period jitter

-75

75

ps

Half-period jitter

-100

100

ps

Output clock slew rate

12

v/ns

Cycle to Cycle Jitter

-75

75

ps

Phase error

4

-50

50

ps

Output to Output Skew

40

60

ps

Rise Time, Fall Time

Load = 120

Ω/16pF

650

800

950

ps

Over the application

frequency range

Notes:

1.

2.

3.

4. Does not include jitter.

Switching characteristics are guaranteed for application frequency range. The PLL

Locks over the Max Clock Frequency range, but the device doe not necessarily

meet other timing parameters.

Refers to transition on noninverting output in PLL bypass mode.

While the pulse skew is almost constant over frequency, the duty cycle error

increases at higher frequencies. This is due to the formula: duty cycle=twH/tc,

were the cycle (tc) decreases as the frequency goes up.