ASM705 / 706 / 707 / 708

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Notice: The information in this document is subject to change without notice

Low Power µP Supervisor Circuits

ASM813L

rev 1.2

July 2004

Pin Description

Pin Number

Name

Function

ASM705/706

ASM707/708

ASM813L

DIP/

SO

MicroSO

DIP/

SO

MicroSO

DIP/

SO

MicroSO

1

3131

3

MR

Manual reset input. The active LOW input triggers a reset

pulse. A 250 µA pull-up current allows the pin to be

driven by TTL/CMOS logic or shorted to ground with a

switch.

2

4242

4

+5V power supply input.

3

5353

5

GND

Ground reference for all signals.

4

6464

6

PFI

Power-fail input voltage monitor. With PFI less than

when not in use.

5

7575

7

PFO

Power-fail output. The output is active LOW and sinks

current when PFI is less than 1.25V.

68

-

-

68

WDI

Watchdog input. WDI controls the internal watchdog

timer. A HIGH or LOW signal for 1.6sec at WDI allows

the internal timer to run-out, setting WDO LOW. The

watchdog function is disabled by floating WDI or by con-

necting WDI to a high impedance three-state buffer. The

internal watchdog timer clears when: RESET is asserted;

WDI is three-stated ; or WDI sees a rising or falling edge.

-

-

6

8

-

-

NC

Not Connected

7

1

7

1

-

-

RESET

Active LOW reset output. Pulses LOW for 200ms when

reset threshold. RESET remains LOW for 200ms after

LOW to HIGH. A watchdog timeout will not trigger

RESET unless WDO is connected to MR.

82

-

-

82

WDO

Watchdog output. WDO goes LOW when the 1.6 second

internal watchdog timer times-out and does not go HIGH

below the reset threshold, WDO goes LOW. Unlike

RESET, WDO does not have a minimum pulse width and

HIGH with no delay.

-

-

8

2

7

1

RESET

Active HIGH reset output. The inverse of RESET. The

ASM813L has only a RESET output.