AD9278BBCZ datasheet(39/45 Pages) AD

39 / 45 page

AD9278

Data Sheet

Rev. A | Page 38 of 44

This interface is flexible enough to be controlled by either serial

PROMs or PIC microcontrollers, providing the user with

an alternative method, other than a full SPI controller, for

programming the device (see the AN-812 Application Note).

DON’T

CARE

DON’T

CARE

DON’T

CARE

DON’T

CARE

SDIO

SCLK

CSB

tDH

tHIGH

tCLK

tLOW

tDS

R/W

A12

A11

A10

Figure 66. Serial Timing Details

Table 18. Serial Timing Definitions

Parameter

Timing (ns min)

Description

tDS

Setup time between the data and the rising edge of SCLK

tDH

Hold time between the data and the rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHIGH

Minimum period that SCLK should be in a logic high state

tLOW

Minimum period that SCLK should be in a logic low state

tEN_SDIO

Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling

edge (not shown in Figure 66)

tDIS_SDIO

Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising

edge (not shown in Figure 66)

AD9278BBCZ 数据表(PDF) 39 Page - Analog Devices

AD9278BBCZ 数据表(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表下载

链接网址

AD9278BBCZ 数据表(PDF) 39 Page - Analog Devices

AD9278BBCZ 数据表(HTML) 39 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

数据表 下载

链接网址

数据表下载