AD9671KBCZ datasheet(49/61 Pages) AD

49 / 61 page

AD9671

Data Sheet

Rev. A| Page 48 of 60

Table 33. AD9671 Memory Map Registers

Addr.

(Hex)

Name

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Default

Value

Comments

Chip Configuration Registers

0x000

CHIP_

PORT_

CONFIG

LSB first

0 = off

(default)

1 = on

SPI reset

0 = off

(default)

1 = on

SPI reset

0 = off

(default)

1 = on

LSB first

0 = off

(default)

1 = on

0x18

Nibbles

mirrored so

that LSB or

MSB first mode

is set correctly,

regardless of

shift mode. SPI

reset reverts

all registers

(including the

JESD ones),

except Reg.

0x000 to their

default values

and Reg. 0x000,

Bit 2 and Bit 5

are auto-

matically

cleared.

0x001

CHIP_ID

Chip ID Bits[7:0]

AD9671 = 0xA7 (default)

0xA7

Default is

unique chip

ID, different

for each

device; read

only register.

0x002

CHIP_

GRADE

Speed mode

(identify device

variants of chip ID)

00: Mode I

(40 MSPS) (default)

01: Mode II (65 MSPS)

10: Mode III (80 MSPS)

11: Mode III (125 MSPS)

0x0X

Speed mode

used to

differentiate

ADC speed

power modes

(must update

Reg. 0x0FF to

initiate mode

setting).

Device Index and Update Registers

0x004

DEVICE_

INDEX_2

Data

Channel H

0 = off

1 = on

(default)

Data

Channel G

0 = off

1 = on

(default)

Data

Channel F

0 = off

1 = on

(default)

Data

Channel E

0 = off

1 = on

(default)

0x0F

Bits are

set to de-

termine which

on-chip device

receives the

next write

command.

0x005

DEVICE_

INDEX_1

Data

Channel D

0 = off

1 = on

(default)

Data

Channel C

0 = off

1 = on

(default)

Data

Channel B

0 = off

1 = on

(default)

Data

Channel A

0 = off

1 = on

(default)

0x3F

Bits are

set to de-

termine which

on-chip device

receives the

next write

command.

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