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DA9213 数据表(PDF) 32 Page - Dialog Semiconductor

部件名 DA9213
功能描述  Multi-Phase 5A/Phase DC-DC Buck Converter
PDF  62 Pages
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制造商  DIALOG [Dialog Semiconductor]
网页  http://www.dialog-semiconductor.com/
标志 DIALOG - Dialog Semiconductor

DA9213 数据表(HTML) 32 Page - Dialog Semiconductor

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DA9213, DA9214, and DA9215
Multi-Phase 5A/Phase DC-DC Buck Converter
Datasheet
Revision 2.2
23-Oct-2017
CFR0011-120-00
32 of 62
© 2017 Dialog Semiconductor
DA9213, DA9214, and DA9215's 4-WIRE interface offers two further configuration bits. Clock polarity
(CPOL) and clock phase (CPHA) define when the interface will latch the serial data bits. CPOL
determines whether SK idles high (CPOL = 1) or low (CPOL = 0). CPHA determines on which SK
edge data is shifted in and out. With CPOL = 0 and CPHA = 0, DA9213, DA9214, and DA9215 latch
data on the SK rising edge. If the CPHA is set to 1 the data is latched on the SK falling edge. CPOL
and CPHA states allow four different combinations of clock polarity and phase. Each setting is
incompatible with the other three. The host and DA9213, DA9214, and DA9215 must be set to the
same CPOL and CPHA states to communicate with each other.
A0
A6
A5
A4
A3
A2
A1
R/Wn
D0
D6
D5
D4
D3
D2
D1
D7
nCS
SK
SI
SO
4-WIRE WRITE
A0
A6
A5
A4
A3
A2
A1
R/Wn
nCS
SK
SI
SO
4-WIRE READ
D0
D6
D5
D4
D3
D2
D1
D7
latch data
HI-Z
Figure 20: 4-
WIRE Host Write and Read Timing (nCS_POL = ‘0’, CPOL = ‘0’, CPHA = ‘0’)



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