Data Sheet

AD830

Rev. D | Page 13 of 20

10

0%

100

90

1V

1V

Figure 30. Clipping Behavior

Choice of Polarity

The sign of the gain is easily selected by choosing the polarity

Swapping between inverting and noninverting gain is possible

simply by reversing the input connections. The response of the

amplifier is identical in either connection, except for the sign

change.

The bandwidth, high impedance, and transient behavior of the

AD830 is symmetrical for both polarities of gain. This is very

advantageous and unlike an op amp.

Input Impedance

The relatively high input impedance of the AD830, for a

differential receiver amplifier, permits connections to modest

impedance sources without much loading or loss of common-

mode rejection. The nominal input resistance is 300 kΩ. The

real limit to the upper value of the source resistance is in its

effect on common-mode rejection and bandwidth. If the source

resistance is in only one input, then the low frequency

resistance/input capacitance pole limits the bandwidth. Refer to

the following equation:













×

×

π

=

IN

S

C

R

f

2

1

Furthermore, the high frequency common-mode rejection is

additionally lowered by the difference in the frequency response

and high frequency common-mode rejection, it is recommended

that the source resistances of the + and − inputs be matched and

of modest value (≤10 kΩ).

Handling Bias Currents

The bias currents are typically 4 μA flowing into each pin of the

finite source resistance, the bias current through this resistor

≤10 kΩ. If the source resistance is in only one terminal, then an

objectionable offset voltage may result, for example, 4 μA × 5

kΩ = 20 mV. Placement of an equal value resistor in series with

the other input cancels the offset to first order. However, due to

mismatches in the resistances, a residual offset remains and is

likely to be greater than the bias current (offset current)

mismatches.

Applying Feedback

The AD830 is intended for use with gains from 1 to 100. Gains

greater than one are simply set by a pair of resistors connected

as shown in the difference amplifier (Figure 40) with gain >1.

it does not introduce excessive phase shift around the loop and

destabilize the amplifier. A compensating resistor, equal to the

common-mode rejection and to lower the offset voltage

induced by the input bias current.

Output Common Mode

The output swing of the AD830 is defined by the differential

input voltage, the gain, and the output common. Depending on

the anticipated signal span, the output common (or ground)

may be set anywhere between the allowable peak output voltage

in a manner similar to that described for input voltage common

mode. A plot of the peak output voltage versus the supply is

shown in Figure 31. A prediction of the common-mode range

versus the peak output differential voltage can be easily derived

SUPPLY VOLTAGE (V)

15

0

20

0

4

8

12

16

6

3

12

9

Figure 31. Maximum Output Swing vs. Supply

Output Current

The absolute peak output current is set by the short-circuit

current limiting, typically greater than 60 mA. The maximum

drive capability is rated at 50 mA but without a guarantee of

distortion performance. Best distortion performance is obtained

by keeping the output current ≤20 mA. Attempting to drive

large voltages into low valued resistances, for example, 10 V into

150 Ω causes an apparent lowering of the limit for output signal

swing but is just the current limiting behavior.