RAMK040 HP

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Vishay MCB

Revision: 06-Dec-17

4

Document Number: 32535

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ELECTRICAL INTERFACE DESCRIPTION - SSI INTERFACE

Note

Timing Diagram

ELECTRICAL INTERFACE DESCRIPTION - SPI INTERFACE (on request)

Timing Diagram

OPTIONS

• Other design on request (mechanical interfaces, electrical interfaces, ...)

6 WIRES CONNECTIONS

NAME

WIRE COLOR

GND

Black

+5 V

Red

CLK+

White

CLK-

Clear

DATA+

Yellow

DATA-

Green

SSI PARAMETERS

Output code

Binary

Data differential interface

RS422 according to EIA-RS422

CLK differential interface

RS422 according to EIA-RS422

Minimum clock frequency

300 kHz

Maximum clock frequency

4 MHz

Data bit (n)

18 bits

Master system

Sensor

+5 V

+5 V

+5 V

+5 V

100

Ω

+5 V

+5 V

GND

+5 V

DATA+

DATA-

CLK-

CLK+

t

1

F

clock

t

≥ 500 ns

t

CLK+

DATA-

CLK-

DATA+

≤ 200 ns

Start of cycle

End of cycle

0

1

2

15

16

17

LSB

MSB

5 WIRES CONNECTIONS

NAME

WIRE COLOR

GND

Black

+5 V

Red

CLK

White

DATA

Clear

CS

Yellow

SPI PARAMETERS

Output code

Binary

Minimum clock frequency

300 kHz

Maximum clock frequency

4 MHz

Data bit (n)

18 bits

Master system

Slave Sensor

+5 V

+5 V

GND

+5 V

DATA

CLK+

CLK

MISO

CLK

Data Out

CS

CS

CS

0

1

2

15

16

17

MSB

LSB

1

F

clock

t

t

t

18

F

clock

t > t

+ t

e

17

16

CS

CLK

DATA