2004 Mar 22

2

Philips Semiconductors

Product specification

Quad 2-input NAND gate (open drain)

74LVC38A

FEATURES

• 5 V tolerant inputs for interfacing with 5 V logic

• Wide supply voltage range from 1.2 to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Open-drain outputs

• Inputs accept voltages up to 5.5 V

• Complies with JEDEC standard no. 8-1A

• Specified from −40 to +85 °C and −40 to +125 °C.

DESCRIPTION

The 74LVC38A is a high-performance, low-power,

low-voltage, Si-gate CMOS device, superior to most

advanced CMOS compatible TTL families.

Inputs can be driven from either 3.3 or 5 V devices. This

feature allows the use of these devices as translators in a

mixed 3.3 and 5 V environment.

The 74LVC38A provides the 2-input NAND function.

The outputs of the 74LVC38A devices are open drain and

can be connected to other open-drain outputs to

implement active-LOW wired-OR or active-HIGH

wired-AND functions.

QUICK REFERENCE DATA

Notes

N = total load switching outputs;

ORDERING INFORMATION

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

propagation delay nA, nB to nY

1.7

ns

propagation delay nA, nB to nY

2.3

ns

input capacitance

4.0

pF

power dissipation capacitance per gate

5.5

pF

TYPE NUMBER

PACKAGE

TEMPERATURE RANGE

PINS

PACKAGE

MATERIAL

CODE

74LVC38AD

−40 to +125 °C

14

SO14

plastic

SOT108-1

74LVC38ADB

−40 to +125 °C

14

SSOP14

plastic

SOT337-1

74LVC38APW

−40 to +125 °C

14

TSSOP14

plastic

SOT402-1

74LVC38ABQ

−40 to +125 °C

14

DHVQFN14

plastic

SOT762-1