| 数据搜索系统,热门电子元器件搜索 |
|
P75N02LS 数据表(PDF) 2 Page - List of Unclassifed Manufacturers |
|
|
|||||||||||||||||||||||||||||
P75N02LS 数据表(HTML) 2 Page - List of Unclassifed Manufacturers |
|
2 / 3 page ![]() 2 AUG-02-2001 N-Channel Logic Level Enhancement Mode Field Effect Transistor P75N02LS TO-263 (D 2PAK) NIKO-SEM On-State Drain Current 1 ID(ON) VDS = 10V, VGS = 10V 70 A VGS = 10V, ID = 30A 5 7 Drain-Source On-State Resistance 1 RDS(ON) VGS = 7V, ID = 24A 6 8 m Ω Forward Transconductance 1 gfs VDS = 15V, ID = 30A 16 S DYNAMIC Input Capacitance Ciss 5000 Output Capacitance Coss 1800 Reverse Transfer Capacitance Crss VGS = 0V, VDS = 15V, f = 1MHz 800 pF Total Gate Charge 2 Qg 140 Gate-Source Charge 2 Qgs 40 Gate-Drain Charge 2 Qgd VDS = 0.5V(BR)DSS, VGS = 10V, ID = 35A 75 nC Turn-On Delay Time 2 td(on) 7 Rise Time 2 tr VDS = 15V, RL = 1Ω 7 Turn-Off Delay Time 2 td(off) ID ≅ 30A, V GS = 10V, RGS = 2.5Ω 24 Fall Time 2 tf 6 nS SOURCE-DRAIN DIODE RATINGS AND CHARACTERISTICS (TC = 25 °C) Continuous Current IS 75 Pulsed Current 3 ISM 170 A Forward Voltage 1 VSD IF = IS, VGS = 0V 1.3 V Reverse Recovery Time trr 37 nS Peak Reverse Recovery Current IRM(REC) IF = IS, dlF/dt = 100A / µS 200 A Reverse Recovery Charge Qrr 0.043 µC 1Pulse test : Pulse Width ≤ 300 µsec, Duty Cycle ≤ 2%. 2Independent of operating temperature. 3Pulse width limited by maximum junction temperature. REMARK: THE PRODUCT MARKED WITH “P75N02LS”, DATE CODE or LOT # |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |