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MB90F548GPF 数据表(PDF) 49 Page - Cypress Semiconductor

部件名 MB90F548GPF
功能描述  CMOS F2MC-16LX MB90540G/545GSeries 16-bit Proprietary Microcontroller
PDF  70 Pages
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

MB90F548GPF 数据表(HTML) 49 Page - Cypress Semiconductor

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Document Number: 002- 07696 Rev. *A
Page 49 of 70
MB90540G/545G Series
11.4.5 Bus Timing (Read)
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC
3.5 V to 5.5 V, V
SS
AV
SS
0.0 V, T
A
  40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC
5.0 V 10, V
SS
AV
SS
0.0 V, T
A
  40 C to 105 C)
Parameter
Symbol
Pin name
Condition
Value
Units
Remarks
Min
Max
ALE pulse width
tLHLL
ALE
tCP/2
20
ns
Valid address
 ALE time
tAVLL
ALE,
A16 to A23,
AD00 to AD15
tCP/2
20
ns
ALE
  Address valid time
tLLAX
ALE, AD00 to
AD15
tCP/2
15
ns
Valid address
 RD time
tAVRL
A16 toA23,
AD00 to AD15,
RD
tCP
15
ns
Valid address
 Valid data
input
tAVDV
A16 to A23,
AD00 to AD15
5 tCP/2
60 ns
RD pulse width
tRLRH
RD
3 tCP/2
20
ns
RD
  Valid data input
tRLDV
RD, AD00 to
AD15
3 tCP/2
60 ns
RD
  Data hold time
tRHDX
RD, AD00 to
AD15
0
ns
RD
  ALE time
tRHLH
RD, ALE
tCP/2
15
ns
RD
  Address valid time
tRHAX
RD, A16 to A23
tCP/2
10
ns
Valid address
 CLK time
tAVCH
A16 to A23,
AD00 to AD15,
CLK
tCP/2
20
ns
RD
  CLK time
tRLCH
RD, CLK
tCP/2
20
ns
ALE
  RD time
tLLRL
ALE, RD
tCP/2
15
ns



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