MB90F548GLSPF datasheet(4/70 Pages) CYPRESS

4 / 70 page

Document Number: 002- 07696 Rev. *A

Page 4 of 70

MB90540G/545G Series

1. Product Lineup

(Continued)

Features

MB90F543G (S) /F548G (S)

MB90F549G (S) /F546G (S)

MB90F548GL(S)

MB90543G (S)

MB90547G (S)

MB90548G (S)

MB90549G (S)

MB90V540G

CPU

F2MC-16LX CPU

System clock

On-chip PLL clock multiplier (

1, 2, 3, 4, 1/2 when PLL stop)

Minimum instruction exection time : 62.5 ns (machine clock 16MHz, 4MHz osc. four times multiplied by PLL)

ROM

Flash memory

MB90F543G(S)/F548G(S) / F548GL(S)

: 128 Kbytes

MB90F549G(S)/F546G(S) :

256 Kbytes

MASK ROM :

MB90547G(S): 64 Kbytes

MB90543G(S)/548G(S): 128

Kbytes

MB90549G(S): 256 Kbytes

External

RAM

MB90F548G(S)/F548GL(S):

4 Kbytes

MB90F543G (S) /F549G(S) :

6 Kbytes

MB90F546G(S) : 8 Kbytes

MB90547G(S): 2 Kbytes

MB90548G(S): 4 Kbytes

MB90543G(S)/549G(S):

6 Kbytes

8 Kbytes

Clocks

MB90F543G/F548G/F549G/F546G/

F548GL :

Two clocks system

MB90F543GS/F548GS/F549GS/

F546GS/F548GLS :

One clock system

MB90543G/547G/548G/549G :

Two clocks system

MB90543GS/547GS/548GS/

549GS :

One clock system

Two clocks system*1

Operating voltage range

Temperature range

40 C to 105 C

Package

QFP100, LQFP100

PGA-256

Emulator-specify

power supply*2



None

UART0

Full duplex double buffer

Support asynchronous/synchronous (with start/stop bit) transfer

Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)

500 K/1 M/2 Mbps (synchronous) at System clock

 16 MHz

UART1

(SCI)

Full duplex double buffer

Asynchronous (start-stop synchronized) and CLK-synchronous communication

Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous)

62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz

Serial I/O

Transfer can be started from MSB or LSB

Supports internal clock synchronized transfer and external clock synchronized transfer

Supports positive-edge and nagative-edge clock synchronization

Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock

 16 MHz

A/D Converter

10-bit or 8-bit resolution

8 input channels

Conversion time : 26.3

s (per one channel)

MB90F548GLSPF 数据表(PDF) 4 Page - Cypress Semiconductor

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