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TCD2000P 数据表(PDF) 4 Page - Toshiba Semiconductor |
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TCD2000P 数据表(HTML) 4 Page - Toshiba Semiconductor |
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4 / 11 page ![]() TCD2000P 2002-03-08 4 Note 7: DC signal output voltage and DC compensation output voltage are defined as follows:. OPERATING CONDITION CHARACTERISTIC SYMBOL MIN TYP. MAX UNIT “H” Level 4.5 5.0 5.5 Master Clock Pulse Voltage “L” Level VφM 0 ― 0.5 V “H” Level 4.5 5.0 5.5 Clock Pulse Voltage “L” Level Vφ1 Vφ2 0 ― 0.5 V “H” Level Vφ−0.5 Vφ Vφ Shift Pulse Voltage “L” Level VSH 0 ― 0.5 V “H” Level 4.5 5.0 13.0 Sample and Hold Switch Voltage* “L” Level VSP 0 ― 0.5 V Reference Voltage VREF 11.4 12.0 13.0 V Power Supply Voltage (Analog) VAD 11.4 12.0 13.0 V VDD1 11.4 12.0 13.0 Power Supply Voltage (Digital) VDD2 11.4 12.0 13.0 V (*) Supply “H” Level to VSP terminal when sample−and−hold circuit is used, when sample−and−hold circuit is not used supply “L” Level to VSP terminal. CLOCK CHARACTERISTICS (Ta = 25°C) CHARACTERISTIC SYMBOL MIN TYP. MAX UNIT Master Clock Pulse Frequency fφM ― 2.0 6.0 MHz Clock Pulse Frequency fφ ― 1.0 3.0 MHz Master Clock Pulse Capacitance CφM ― 10 20 pF Clock Capacitance Cφ ― 100 200 pF Shift Gate Capacitance CSH ― 50 100 pF |
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