Preliminary Data Sheet

AC101L

8/9/04

B roa dcom Co rpo rat ion

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AC101L-DS06-R

Clock Source

Page 11

The clock source for this chip is from the XI pin. In MII mode, it can connect to a 25 MHz 50 ppm (parts per million) OSC or

a 25 MHz 50 ppm XTAL (crystal).

When the AC101L device is put into isolate mode, all MII inputs (TXD[3:0}, TXEN, TXER) are ignored, and all MII outputs

(TX_CLK, COL, CRS, RX_CLK, RXDV, RXER, RXD[3:0] are set to high impedance. Only the MII management pins (MDC,

MDIO) operate normally. Pull HIGH pin 4 at reset or write 1 to bit 10 register 0 to put the chip into isolate mode.

Local loopback is provided for testing purpose. It can be enabled by writing a one to register 0 bit 14.

The local loopback routes transmitted data through the transmit path back to the clock and data recovery module of the

receiving path. The loopback data are presented to the PCS in 5-bit symbol format. This loopback is used to check the

operation of the 5-bit symbol decoder and the phase lock loop circuitry. In local loopback, the SD output is forced to a logical

1 and TXOP/N outputs are tristated.

The INTR pin on the PHY is asserted whenever 1 of 8 selectable interrupt events occurs. The assertion state is high or low

and is programmable through the INTR_LEVL register bit. The selection is made by setting the appropriate bit in the upper

half of the Interrupt Control/Status register. When the INTR bit goes active, the MAC interface is required to read the Interrupt

Control/Status register to determine which event caused the interrupt. The Status bits are read-only and clear-on-read.

When INTR is not asserted, the pin is held in a high impedance state.

The LED interface is fully configurable through register setting. The connection of LED (source/sink current) depends on the

default setting.