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AC101L-DS03-R 数据表(PDF) 34 Page - Broadcom Corporation. |
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AC101L-DS03-R 数据表(HTML) 34 Page - Broadcom Corporation. |
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34 / 54 page ![]() AC101L Preliminary Data Sheet 8/9/04 B roa dcom Co rpo rat ion Page 24 Common Registers Document AC101L-DS06-R COMMON REGISTER 6: (MAP TO REG. 31, PAGE 1 A.28.[15:12]=0001) LED0 SETTING2 REGISTER COMMON REGISTER 7: (MAP TO REG. 29, PAGE 2 A.28.[15:12]=0010) LED1 SETTING1 REGISTER COMMON REGISTER 8: (MAP TO REG. 30, PAGE 2 A.28.[15:12]=0010) LED1 SETTING2 REGISTER Default Operation for LED1 is ON during 100 Mbps operation. COMMON REGISTER 9: (MAP TO REG. 31, PAGE 2 A.28.[15:12]=0010) LED2 SETTING1 REGISTER Table 26: Common Register 6: (Map to Reg. 31, Page 1 A.28.[15:12]=0001) LED0 Setting2 Register Bit Name Description Mode Default A1.31. [15:8] Msk On On mask. When the bits are set to 1, a corresponding event causes the LED to turn on. RW 00000001 A1.31. [7:0] Msk Off Off mask. When the bits are set to 1, a corresponding event causes the LED to turn off. RW 00000000 Table 27: Common Register 7: (Map to Reg. 29, Page 2 A.28.[15:12]=0010) LED1 Setting1 Register Bit Name Description Mode Default A2.29.[15:13] Reserved – RO 000 A2.29.12 Force LED On Forces LED1 on. RW 0 A2.29.[11:9] Reserved – RO 000 A2.29.8 Force LED Off Forces LED1 off. RW 0 A2.29.[7:0] Msk Blink Blink mask. When the bits are set to 1, a corresponding event causes the LED to blink. RW 00000000 Table 28: Common Register 8: (Map to Reg. 30, Page 2 A.28.[15:12]=0010) LED1 Setting2 Register Bit Name Description Mode Default A2.30.[15:8] Msk On On mask. When the bits are set to 1, a corresponding event causes the led to turn on. RW 00100000 A2.30.[7:0] Msk Off Off mask. When the bits are set to one, a corresponding event causes the led to turn off. RW 00000000 Table 29: Common Register 9: (Map to Reg. 31, Page 2 A.28.[15:12]=0010) LED2 Setting1 Register Bit Name Description Mode Default A2.31.[15:13] Reserved – RO 000 A2.31.12 Force LED On Forces LED2 on. RW 0 A2.31.[11:9] Reserved – RO 000 A2.31.8 Force LED Off Forces LED2 off. RW 0 |
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