5220-DS03-R datasheet(22/90 Pages) BOARDCOM

22 / 90 page

BCM5220

Preliminary Data Sheet

04/20/04

Broa d c om Co rp o r a t i o n

Page 10

MII Management

Document

5220-DS04-405-R

SPDLED#

ADV_PAUSE#

TMS

I/OPU

100BASE-X LED. The 100BASE-X LED is driven low when

operating in 100BASE-X modes and high when operating in

10BASE-T modes. When bit 12 of register 1Dh is set to 1,

SPDLED# is driven low when the 100BASE-T link is good.

ADV_PAUSE#. Active low. During power-on reset, this pin is

sampled and causes the default value of MII auto-negotiation

Advertisement register, 4, bit 10d to be set accordingly.

Test Mode Select. This pin becomes TMS if JTAG_EN is high.

Single control input to the JTAG TAP controller is used to

traverse the test-logic state machine. Sampled on the rising edge

of TCK.

XMTLED#

INTR#

FDXLED#

OOD

Transmit Activity LED. Active low output. The transmit activity

LED is driven low for approximately 80 ms each time there is

transmit activity while in the link pass state. When the interrupt

mode is enabled, pin becomes INTR#. When FDXLED mode is

enabled, pin becomes FDXLED#.

RCVLED#

ACTLED#

TDO

I/OPU

Receive Activity LED. Active low output. The receive activity

LED is driven low for approximately 80 ms each time there is

receive activity while in the link pass state. In either interrupt or

FDXLED mode, pin becomes ACTLED#, indicating both receive

and transmit activity.

Test Data Output. This pin becomes TDO if JTAG_EN is high.

Serial data output from the JTAG TAP controller. Updated on the

falling edge of TCK.

JTAG

JTAG_EN

IPD

JTAG Enable. Active high. When high causes the BCM5220 to

enter JTAG test mode. For normal operation leave this pin

unconnected.

Power

REGDVDD

PWR

Digital Voltage Regulator Input. Connect this pin to a digital

3.3V supply.

REGAVDD

PWR

Analog Voltage Regulator Input. Connect this pin to an analog

3.3V supply.

C3, C5

2, 55

DVDD

PWR

Digital Regulator output (2.5V). Connect these pins to

decoupling capacitors as shown in Figure 18 on page 73.

F4, F5

27, 28

AVDD

PWR

Analog Regulator output VDD (2.5V). Connect these pins to

decoupling capacitors as shown in Figure 18 on page 73.

B2, E7,

1, 46, 18

OVDD

PWR

3.3V Digital Periphery (Output Buffer) VDD supply.

C7, D4,

D6, E5

40, 45

54, 63

DGND

GND

Digital Ground.

G6, H6

29, 32

AGND

GND

Analog Ground.

XTALGND

GND

Crystal Ground.

BIASVDD

PWR

BIAS VDD. Connect this pin to AVDD.

BIASGND

GND

Bias Ground. Connect this pin to AGND.

OVDD/NC

PWR

This pin is for factory test only. For normal operation, leave this

pin unconnected or connect to OVDD supply

Table 3: Pin Descriptions (Cont.)

5220KPB 5220KPT

Pin Label

Type

Description

[MSB:LSB]; # = active-low signal, I = input, O = output, I/O = bidirectional, IPU = input w/ internal pull-up, OOD = open-drain

output, O3S = three-state output, B = Bias, PWR = power supply, GND = ground

5220-DS03-R 数据表(PDF) 22 Page - Broadcom Corporation.

5220-DS03-R 数据表(HTML) 22 Page - Broadcom Corporation.

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