Production Specification

07/03/02

B roa dcom Co rpo rat ion

Section 1: Functional Description...................................................................................... 1

Overview ........................................................................................................................................................ 1

Key Features and Statistics ........................................................................................................................... 1

Streamlined Hardware Interface ............................................................................................................. 1

IETF IPsec Compliant Acceleration ........................................................................................................ 2

IETF IKE ................................................................................................................................................. 2

Secure Socket Layer (SSL) v 3.0, Transport Layer Security (TLS) ........................................................ 2

Streamlined, Flexible Software Command and Packet Interface............................................................ 2

Additional Performance Enhancing Features ......................................................................................... 2

Advanced Testability Features................................................................................................................ 2

BCM5802 Additional Features to BCM5801 ........................................................................................... 3

Optimal Application Areas .............................................................................................................................. 3

Processing Overview ..................................................................................................................................... 3

Section 2: Hardware System Interface and Performance ................................................ 6

Application Examples ..................................................................................................................................... 6

Hardware Interface......................................................................................................................................... 7

Support for Both PCI 3.3V and PCI 5V Signaling Environments ..................................................... 7

Latency Tolerant Design .................................................................................................................. 7

Support for PCI Clock Rates from 25-33 MHz ................................................................................. 7

In-System Performance Analysis ................................................................................................................... 8

Section 3: Hardware Signal Definition Table..................................................................... 9

Pinout Diagram ............................................................................................................................................ 11

Section 4: Software Programming Model........................................................................ 12

Overview of Software Interface .................................................................................................................... 12

Memory Structures ....................................................................................................................................... 14

IPsec Crypto/Authentication Processing Data Structure....................................................................... 14

IKE/SSL/TLS Key Setup Processing Data Structure ............................................................................ 16

Pictorial Illustrations of Memory Structures........................................................................................... 19

IPsec ESP and AH (Bulk Encryption and Authentication) Processing........................................... 19

Key Setup Processing ................................................................................................................... 22

Alignment Restrictions ................................................................................................................................. 32