5228-DS06-R datasheet(18/100 Pages) BOARDCOM

18 / 100 page

BCM5228

Data Sheet

7/12/04

Broa d c om Co rp o r a t i o n

Page 6

MII Management

Document

5228-DS09-405-R

http://www.rmii-consort.com. The purpose of this interface is to provide a low-cost alternative to the IEEE 802.3u[2] Media

Independent Interface (MII). The RMII is capable of supporting 10 megabit and 100 megabit data rates with a single clock,

using independent 2-bit wide transmit and receive paths.

A single 50-MHz synchronous reference clock is used as a timing reference for all transmitters and receivers. By doubling

the clock frequency relative to the MII, four pins are saved in the data path, which uses two lines into each transmitter and

two lines out of each receiver, compared to four lines used in each direction in the MII. Since start-of-packet and end-of-

packet timing information is preserved across the interface, the MAC is able to derive the COL signal from the receive and

transmit data delimiters, saving another pin.

Transmit and receive clocks have been eliminated as well. All data transfers are synchronous with REF_CLK. This poses

less of a challenge for the transmitter than it does for the receiver, which is now required to buffer output data in a FIFO until

an edge of the REF_CLK is suitably aligned. The received data bits and the RX_DV signal are passed through the FIFO,

but the CRS_DV bit is not. It is asserted for the time the wire is receiving a frame. If the remote transmitter is idle, and no

data need be passed from the receiver, status information can be made available by setting Bit 1 of register 10h. Out-of-

band signaling consists of 2 di-bit pairs immediately following the last di-bit pair of a received packet. The 2 di-bit pairs consist

of full-duplex, Link Speed - msb, lsb and RXER, FIFO Error - msb, lsb.

MII MANAGEMENT

Management of each transceiver within the BCM5228 remains the same as it was under the MII specification. Each PHY

contains an independent set of MII management registers. They share a single MDC/MDIO serial interface. Each transceiver

has a unique address and must be accessed individually. The common base address for the group of eight individual

transceivers is defined by configuring the five external PHYAD address input pins.

SERIAL MEDIA INDEPENDENT INTERFACE (SMII)

The SMII is an alternative to both the MII and RMII. The objective is to reduce the number of pins required to interconnect

the MAC and the PHY. This is accomplished by clocking data and control signals in and out of each PHY on a pair of pins

at a rate of 125 MHz. The SMII mode is selected by pulling the SMII_EN pin high during power-on reset.

Data and control signals passing from the MAC to the PHY use the serial transmit (STX) line. Data and control signals

passing from the PHY to the MAC use the serial receive (SRX) line. All bit transfers are synchronous with clock (SCLK) at

125 MHz. Frame synchronization is provided by a fourth line (SYNC), asserted at the beginning of each frame, which occurs

every 10 cycles of SCLK. Each PHY is provided with an STX and an SRX pair. Pins TXD0{x} and RXD0{x}, where x is the

number of the specific PHY, are used to perform the STX and SRX functions.

The BCM5228 chip has a single SCLK and SYNC input that is common to all PHYs. Pins REF_CLK and SSYNC are used

for these functions.

Receive data and control information are passed from the PHY to the MAC in 10 bit frames. In 100 Mbps mode, each frame

represents a new byte of data. In 10 Mbps mode, each byte of data is repeated 10 times. The MAC can sample any one of

every 10 frames. Since the timing of data coming from a remote transmitter is not synchronized with the local SCLK or SYNC

lines and can contain errors in frequency, a FIFO capable of storing 28 bits is provided in each receive path. The received

data bits and the RX_DV signal are passed through the FIFO, but the CRS bit is not. It is asserted for the time the wire is

receiving a frame. If the remote transmitter is idle and no data need be passed from the receiver, status information becomes

available.

5228-DS06-R 数据表(PDF) 18 Page - Broadcom Corporation.

5228-DS06-R 数据表(HTML) 18 Page - Broadcom Corporation.

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