DS3152N datasheet(35/60 Pages) DALLAS

35 / 60 page

DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

35 of 60

12.3 JTAG Instruction Register and Instructions

The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the

TAP controller enters the Shift-IR state, the instruction shift register is connected between JTDI and JTDO. While in

the Shift-IR state, a rising edge on JTCLK with JTMS low shifts data one stage toward the serial output at JTDO. A

rising edge on JTCLK in the Exit1-IR state or the Exit2-IR state with JTMS high moves the controller to the Update-

IR state. The falling edge of that same JTCLK latches the data in the instruction shift register to the instruction

parallel output. Table 12-A shows the instructions supported by the DS315x and their respective operational binary

codes.

Table 12-A. JTAG Instruction Codes

INSTRUCTIONS

SELECTED REGISTER

INSTRUCTION CODES

SAMPLE/PRELOAD

Boundary Scan

010

BYPASS

Bypass

111

EXTEST

Boundary Scan

000

CLAMP

Bypass

011

HIGHZ

Bypass

100

IDCODE

Device Identification

001

SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This

instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register

without interfering with the device’s normal operation by using the Capture-DR state. SAMPLE/PRELOAD also

allows the DS315x to shift data into the boundary scan register through JTDI using the Shift-DR state.

EXTEST. EXTEST allows testing of the interconnections to the device. When the EXTEST instruction is latched in

the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs

of the digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The

Capture-DR samples all digital inputs into the boundary scan register.

BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO

through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s

normal operation.

IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test

JTCLK, following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially

through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel

output.

HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI

and JTDO.

CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass

Table 12-B. JTAG ID Code

PART

REVISION

DEVICE CODE

MANUFACTURER CODE

REQUIRED

DS3154

Consult factory

0000000000110011

00010100001

DS3153

Consult factory

0000000000110010

00010100001

DS3152

Consult factory

0000000000110000

00010100001

DS3151

Consult factory

0000000000100000

00010100001

DS3152N 数据表(PDF) 35 Page - Dallas Semiconductor

DS3152N 数据表(HTML) 35 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表下载

链接网址

DS3152N 数据表(PDF) 35 Page - Dallas Semiconductor

DS3152N 数据表(HTML) 35 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

数据表 下载

链接网址

数据表下载