AM29PL320DB90 datasheet(13/50 Pages) SPANSION

13 / 50 page

October 2, 2003

Am29PL320D

Writing Commands/Command Sequences

To write a command or command sequence (which in-

cludes programming data to the device and erasing

sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the WORD# input determines

whether the device accepts program data in double

words or words. Refer to “Word/Double Word Configu-

ration” for more information.

The device features an Unlock Bypass mode to facili-

tate faster programming. Once the device enters the

Unlock Bypass mode, only two write cycles are required

to program a word or double word, instead of four. The

“Word/Double Word Program Command Sequence”

section has details on programming data to the device

using both standard and Unlock Bypass command

sequences.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. Table 4 indicates the address

space that each sector occupies. A “sector address”

consists of the address bits required to uniquely select

a sector. The “Command Definitions” section has de-

ta ils on eras ing a s ect or or the en tire ch ip, or

suspending/resuming the erase operation.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode. The

system can then read autoselect codes from the inter-

nal register (which is separate from the memory array)

on DQ7–DQ0. Standard read cycle timings apply in this

mode. Refer to the “Autoselect Mode” and “Autoselect

Command Sequence” sections for more information.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The “AC

Characteristics” section contains timing specification

tables and timing diagrams for write operations.

Accelerated Program Operation

The device offers accelerated program operations

through the ACC function. This function is primarily in-

tended to allow faster manufacturing throughput dur-

ing system production.

If the system asserts VHH (11.5 to 12.5 V) on this in-

put, the device automatically enters the aforemen-

tioned Unlock Bypass mode, temporarily unprotects

any protected sectors, and uses the higher voltage on

the pin to reduce the time required for program opera-

tions. The system would use a two-cycle program

command sequence as required by the Unlock Bypass

mode. Removing VHH from the ACC pin returns the

device to normal operation.

Note that the ACC pin

must not be at VHH for operations other than acceler-

ated programming, or device damage may result. In

addition, the ACC pin must not be left floating or un-

connected; inconsistent behavior of the device may re-

sult.

Program and Erase Operation Status

During an erase or program operation, the system may

check the status of the operation by reading the status

bits on DQ7–DQ0. Standard read cycle timings and

ICC read specifications apply. Refer to “Write Operation

Status” for more information, and to “AC Characteris-

tics” for timing diagrams.

Standby Mode

When the system is not reading or writing to the de-

vice, it can place the device in the standby mode. In

this mode, current consumption is greatly reduced,

and the outputs are placed in the high impedance

state, independent of the OE# input.

The device enters the CMOS standby mode when the

CE# input is both held at VCC ± 0.3 V. (Note that this is

a more restricted voltage range than VIH.) If CE# is

held at VIH, but not within VCC ± 0.3 V, the device will

be in the standby mode, but the standby current will be

greater. The device requires standard access time

(tCE) for read access when the device is in either of

these standby modes, before it is ready to read data.

If the device is deselected during erasure or program-

ming, the device draws active curren t until the

operation is completed.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device en-

ergy consumption. The device automatically enables this

mode when addresses remain stable for tACC + 30 ns.

The automatic sleep mode is independent of the CE#,

WE#, and OE# control signals. Standard address access

timings provide new data when addresses are changed.

While in sleep mode, output data is latched and always

available to the system. Note that during Automatic Sleep

mode, OE# must be at VIH before the device reduces cur-

rent to the stated sleep mode specification.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The output inputs are placed in the high im-

pedance state.

AM29PL320DB90 数据表(PDF) 13 Page - SPANSION

AM29PL320DB90 数据表(HTML) 13 Page - SPANSION

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

数据表下载