LP28400A – 02

Sep.-2016

www.lowpowersemi.com

Page 2 of 10

Preliminary Datasheet

LP28400A

Functional Pin Description

THM

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Top View

FULL

STAT

REG

VL

VIN

EN

PB

17

GNDP

4

3

2

1

5

6

7

8

RS

STAT

VIN

LX

REG

VBAT

PB

VL

GND

9

TOP VIEW

Pin Description

QFN-16

ESOP8

Pin Name

I/O

Description

1

8

PB

O

Gate control signal for pass transistor also the compensation for Boost.

2

EN

I

Enable pin, active high.

3

1

VIN

I

Power input.

4

2

VL

O

Internal LDO output. Connect a decoupling 4.7uF capacitor to GNDP.

5

LG

O

Low side gate driver for outside power mosfet.

6

3

LX

P

Switching Node Connection.

7,17

9

GNDP

P

Ground for Power section.

8

GNDA

P

Ground for the analog circuits.

9

THM

I

Thermistor

input.

If

the

charging

is

inhibited.

If

the

charger

operates

normally.

If

10

FULL

O

Battery full indication pin, active low.

11

4

STAT

O

Indicates charge status. Active low when charging is on.

12

5

REG

I

Input voltage feedback for the input voltage regulation loop.

13

VB

I

Programmable battery-full voltage. Connect to GND for 4.4V,leave floating to

4.2V, and connect to VL for 4.35V

14

CELLS

I

Cell selection. Connect to GND for 3 cells, leave floating to 2 cells, and connect

to VL for 4 cells.

15

6

RS

I

Indicates charging terminated.

16

7

VBAT

I

Sense pin for battery voltage.