PIC16F819 datasheet(39/176 Pages) MICROCHIP

39 / 176 page

 2004 Microchip Technology Inc.

DS39598E-page 37

PIC16F818/819

4.5.3

OSCILLATOR CONTROL REGISTER

The OSCCON register (Register 4-2) controls several

aspects of the system clock’s operation.

The Internal Oscillator Select bits, IRCF2:IRCF0, select

the frequency output of the internal oscillator block that

is used to drive the system clock. The choices are the

INTRC source (31.25 kHz), the INTOSC source

(8 MHz) or one of the six frequencies derived from the

INTOSC postscaler (125 kHz to 4 MHz). Changing the

configuration of these bits has an immediate change on

the multiplexor’s frequency output.

4.5.4

MODIFYING THE IRCF BITS

The IRCF bits can be modified at any time regardless of

which clock source is currently being used as the

system clock. The internal oscillator allows users to

change the frequency during run time. This is achieved

by modifying the IRCF bits in the OSCCON register.

The sequence of events that occur after the IRCF bits

are modified is dependent upon the initial value of the

IRCF bits before they are modified. If the INTRC

(31.25 kHz, IRCF<2:0> = 000) is running and the IRCF

bits are modified to any other value than ‘000’, a 4 ms

(approx.) clock switch delay is turned on. Code execu-

tion continues at a higher than expected frequency

while the new frequency stabilizes. Time sensitive code

should wait for the IOFS bit in the OSCCON register to

become set before continuing. This bit can be

monitored to ensure that the frequency is stable before

using the system clock in time critical applications.

If the IRCF bits are modified while the internal oscillator

is running at any other frequency than INTRC

(31.25 kHz, IRCF<2:0>

≠ 000), there is no need for a

4 ms (approx.) clock switch delay. The new INTOSC

frequency will be stable immediately after the eight

falling edges. The IOFS bit will remain set after clock

switching occurs.

4.5.5

CLOCK TRANSITION SEQUENCE

WHEN THE IRCF BITS ARE

MODIFIED

Following are three different sequences for switching

the internal RC oscillator frequency.

• Clock before switch: 31.25 kHz (IRCF<2:0> = 000)

1. IRCF bits are modified to an INTOSC/INTOSC

postscaler frequency.

2. The clock switching circuitry waits for a falling

edge of the current clock, at which point CLKO

is held low.

3. The clock switching circuitry then waits for eight

falling edges of requested clock, after which it

switches CLKO to this new clock source.

4. The IOFS bit is clear to indicate that the clock is

unstable and a 4 ms (approx.) delay is started.

Time dependent code should wait for IOFS to

become set.

5. Switchover is complete.

• Clock before switch: One of INTOSC/INTOSC

postscaler (IRCF<2:0>

≠ 000)

1. IRCF

bits

are

modified

INTRC

(IRCF<2:0> = 000).

2. The clock switching circuitry waits for a falling

edge of the current clock, at which point CLKO

is held low.

3. The clock switching circuitry then waits for eight

falling edges of requested clock, after which it

switches CLKO to this new clock source.

4. Oscillator switchover is complete.

• Clock before switch: One of INTOSC/INTOSC

postscaler (IRCF<2:0>

≠ 000)

1. IRCF bits are modified to a different INTOSC/

INTOSC postscaler frequency.

2. The clock switching circuitry waits for a falling

edge of the current clock, at which point CLKO

is held low.

3. The clock switching circuitry then waits for eight

falling edges of requested clock, after which it

switches CLKO to this new clock source.

4. The IOFS bit is set.

5. Oscillator switchover is complete.

Note:

Caution must be taken when modifying the

IRCF bits using BCF or BSF instructions. It

is possible to modify the IRCF bits to a

frequency that may be out of the VDD spec-

ification range; for example, VDD = 2.0V

and IRCF = 111 (8 MHz).

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