Preliminary Technical Data

WM8766

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PTD Rev 2.3 February 2004

21

DAC OUTPUT PHASE

The DAC Phase control word determines whether the output of each DAC is non-inverted or inverted

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Bit

DAC

Phase

0

DAC1L/R

1 = invert

1

DAC2L/R

1 = invert

0000011

DAC Phase

8:6

PHASE

[2:0]

000

2

DAC3L/R

1 = invert

DIGITAL ZERO CROSS-DETECT

The Digital volume control also incorporates a zero cross detect circuit which detects a transition

through the zero point before updating the digital volume control with the new volume. This is

enabled by control bit DZCEN.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

DAC Control

0

ZCD

0

DAC Digital Volume Zero Cross

Enable:

0: Zero cross detect enabled

1: Zero cross detect disabled

MUTE FLAG OUTPUT

The DZFM control bits allow the selection of the six DAC channel zero flag bits for output on the

MUTE pin. A ‘1’ on MUTE indicates 1024 consecutive zero input samples to the DAC channels

selected.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

Zero Flag

2:1

DZFM[1:0]

00

Selects MUTE flag for output on the

MUTE pin (A ‘1’ indicates 1024

consecutive zero input samples on

the DAC channels selected.

00: All channels zero

01: Channel 1 zero

10: Channel 2 zero

11: Channel 3 zero

DZFM[1:0]

MUTE

00

All channels zero

01

Channel 1 zero

10

Channel 2 zero

11

Channel 3 zero

DAC MUTE MODES

The WM8766 has individual mutes for each of the three DAC channels. Setting MUTE for a channel

will apply a ‘soft’ mute to the input of the digital filters of the channel muted.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0001001

DAC Mute

5:3

DMUTE

[2:0]

000

DAC Soft Mute Select