MP1475 – SYNCHRONOUS STEP-DOWN CONVERTER

MP1475 Rev. 1.01

www.MonolithicPower.com

9

4/3/2014

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OPERATION

The MP1475 is a high-frequency, synchronous,

rectified, step-down, switch-mode converter

with built-in power MOSFETs. It offers a very

compact solution that achieves a 3A continuous

output current with excellent load and line

regulation over a wide input supply range.

The MP1475 operates in a fixed-frequency,

peak-current–control mode to regulate the

output voltage. An internal clock initiates a

PWM cycle. The integrated high-side power

MOSFET turns on and remains on until the

current reaches the value set by the COMP

voltage. When the power switch is off, it

remains off until the next clock cycle starts. If,

within 95% of one PWM period, the current in

the power MOSFET does not reach the value

set by the COMP value, the power MOSFET is

forced to turn off.

Internal Regulator

A 5V internal regulator powers most of the

the output decreases, and the part requires a

0.1µF ceramic decoupling capacitor.

Error Amplifier

The error amplifier compares the FB pin voltage

outputs a current proportional to the difference

between the two. This output current then

charges

or

discharges

the

internal

compensation network to form the COMP

voltage, which controls the power MOSFET

current. The optimized internal compensation

network minimizes the external component

counts and simplifies the control loop design.

Enable/SYNC control

EN/SYNC is a digital control pin that turns the

regulator on and off. Drive EN high to turn on

the regulator; drive it low to turn it off. An

internal 1MΩ resistor from EN/SYNC to GND

allows EN/SYNC to be floated to shut down the

chip.

The EN pin is clamped internally using a 6.5V

series-Zener-diode as shown in Figure 2.

Connecting the EN input pin through a pullup

resistor to the voltage on the IN pin limits the

EN input current to less than 100µA.

≥ (12V – 6.5V) ÷ 100µA = 55kΩ.

Connecting the EN pin is directly to a voltage

source without any pullup resistor requires

limiting the amplitude of the voltage source to

≤6V to prevent damage to the Zener diode.

Figure 2: 6.5V Zener Diode Connection

For external clock synchronization, connect a

clock with a frequency range between 200kHz

and 2MHz 2ms after the output voltage is set:

The internal clock rising edge will synchronize

with the external clock rising edge. Select an

external clock signal with a pulse width less

Under-Voltage Lockout (UVLO)

The MP1475 has under-voltage lock-out

protection (UVLO). When the VCC voltage

exceeds the UVLO rising threshold voltage, the

MP1475 will power up. It shuts off when the

VCC voltage drops below the UVLO falling

threshold voltage. This is non-latch protection.

The MP1475 is disabled when the input voltage

falls below 3.25V. If an application requires a

higher under-voltage lockout (UVLO) threshold,

use the EN pin as shown in Figure 3 to adjust

the input voltage UVLO by using two external

resistors. For best results, set the UVLO falling

threshold (VSTOP) above 4.5V using the

enable resistors. Set the rising threshold

(VSTART) to provide enough hysteresis to

allow for any input supply variations.