MP9928—4V TO 60V SYNCHRONOUS STEP-DOWN CONTROLLER

MP9928 Rev. 1.0

www.MonolithicPower.com

21

5/20/2016

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COMP

R5

C6

C7

Figure 7: COMP External Compensation

The system has two important poles: one from

the compensation capacitor (C6) and the output

resistor of error amplifier and the other tone from

the output capacitor and the load resistor. These

poles can be calculated by:

O

m

P1

A

C6

2

π

G

f

×

×

=

LOAD

P2

R

Co

2

π

1

f

×

×

=

500

μA/V, and Co is the output capacitor.

The system has one important zero due to the

compensation capacitor and the compensation

resistor (R5). This zero is located at:

R5

C6

2

π

1

f

Z1

×

×

=

The system may have another significant zero if

the output capacitor has a large capacitance or a

high ESR value. This zero can be located at:

ESR

ESR

R

Co

2

π

1

f

×

×

=

In this case, a third pole set by the compensation

capacitor (C7) and the compensation resistor can

compensate for the effect of the ESR zero. This

pole is calculated by:

R5

C7

2

π

1

f

P3

×

×

=

The goal of the compensation design is to shape

the converter transfer function for a desired loop

gain. The system crossover frequency where the

feedback loop has unity gain is important, since

lower crossover frequencies result in slower line

and

load

transient

responses,

and

higher

crossover frequencies lead to system instability.

Follow

the

below

steps

to

design

the

compensation:

1. Choose R5 to set the desired crossover

frequency:

FB

OUT

CS

m

C

V

V

G

G

f

Co

2

π

R5

×

×

×

×

=

2. Choose C6 to achieve the desired phase

margin.

For

applications

with

typical

inductor values, set the compensation zero

margin. C6 is then:

C

f

R5

2

π

4

C6

×

×

>

3. C7 is required if the ESR zero of the output

following relationship is valid:

2

f

R

Co

2

π

1

SW

ESR

<

×

×

If this is the case, use C7 to set the pole

Determine C7:

R5

R

Co

C7

ESR

×

=

PCB Layout Considerations

For a controller, the layout is always an important

step in design. A poor layout would result in

reduced performance, EMI problems, resistive

loss and even system instability. Following step

would help to guarantee a good layout design:

1. Input power loop between input capacitor,

high-side MOSFET and low-side MOSFET

should be as small as possible, SW trace

should be as possible as short and wide. At

the

same

time,

one

small

decoupling

capacitor should be placed close to the IC’s

IN and GND pins.

2. Feedback loop should be far away from noise

source such as SW trace, the feedback

divider

resistor

should be as close as

possible to FB and GND pin.