MP8756GD datasheet(13/22 Pages) MPS

13 / 22 page

MP8756 – 26V, 6A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP8756 Rev. 1.1

www.MonolithicPower.com

4/13/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

DC Auto-Tune Loop

The MP8756 applies a DC auto-tune loop to

balance the DC error between VFB and VREF by

adjusting the comparator input REF to make VFB

follow VREF. This is a slow loop, so the load and

line regulation improve without affecting the

transient performance. The relationship between

VFB, VREF, and REF is shown in Figure 4.

Figure 4: DC Auto-Tune Loop Operation

External Ramp for Low Output Voltage

The

MP8756

uses

internal

ramp

compensation control scheme to improve stability

with a pure ceramic output capacitor. In some

operating cases, the internal ramp amplitude is

not sufficient to make the loop stable with

ceramic capacitors. Therefore, an extra external

ramp

around

20mV

needed

for

loop

stabilization. Please refer to the Component

Selection section on page 15 for details.

Large Duty Operation

The MP8756 can support larger duty operations

with its internal TON extension function. When the

part detects that FB is lower than VREF, and VIN -

VOUT < 2V, TON and the duty cycle can be

extended. TON stops extending if FB is greater

than REF or if TON meets its limitation.

Light-Load Ultrasonic Mode (USM)

Ultrasonic mode (USM) is used to keep the

switching frequency above audible frequency

areas during light-load or no-load conditions.

Once the part detects that both the HS-FET and

LS-FET are off for about 32µs, TON shrinks to

keep VOUT under regulation with optimal

efficiency. If the load continues reducing, then

the part discharges VOUT to ensure that FB is

smaller than 102% of the internal reference. The

HS-FET turns on again once the internal FB

reaches VREF and then stops switching.

USM is selected by the MODE setting. Float

MODE to operate the MP8756 in PFM mode with

USM in light-load condition.

Configuring the EN Control

To start up the MP8756 automatically, pull EN up

to the input voltage through a resistive voltage

divider. Please refer to the UVLO Protection

Section on page 14 for details.

MODE Selection

MODE is used to select the MP8756’s working

mode. Pull MODE higher than 2.6V to operate

the MP8756 in forced PWM mode. Float MODE

to operate the MP8756 in PFM mode with USM

at light load. Connect MODE to ground to

operate the MP8756 in PFM mode without USM.

Soft Start (SS)

The

MP8756

employs

soft-start

(SS)

mechanism to ensure a smooth output during

power-up. When EN rises high, the internal

reference voltage and the output voltage ramp up

gradually. Once the reference voltage reaches its

target value, the soft start finishes and the circuit

enters steady-state operation.

If the output is pre-biased to a certain voltage

during start-up, the IC disables the switching of

both the high-side and low-side switches until the

voltage on the internal reference exceeds the

sensed output voltage at the internal FB node.

Power Good (PG)

The MP8756 uses a power good (PG) output to

indicate whether the output voltage of the buck

regulator is ready or not. PG is the open drain of

the MOSFET and should be connected to VCC

or another voltage source through a resistor (e.g.:

100k). After the input voltage is applied, the

MOSFET is turned on and PG is pulled to GND

before SS is ready. Once the FB voltage reaches

95% of VREF, PG is pulled high after a 500µs

delay. When the FB voltage drops to 85% of VREF,

PG is pulled low. When the output voltage is

higher than 115% of the internal reference, PG is

pulled low. PG rises high again after the output

voltage drops below 105% of the internal

reference voltage.

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