MP8005 – IEEE 802.3af PoE POWERED DEVICE CONTROLLER

MP8005 Rev. 1.0

www.MonolithicPower.com

9

9/26/2013

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© 2013 MPS. All Rights Reserved.

OPERATION

The MP8005 operates in the manner described

here and in the IEEE 802.3af Powered Device

(PD) Specification. This device (along with the

power sourcing element (PSE)) operates as a

safety device to supply potentially lethal voltages

only

when

the

power

sourcing

element

recognizes a unique, tightly specified resistance

at the end of an unknown length of Ethernet

cable.

A 25kΩ resistance is presented as a load to the

PSE in Detection Mode, when the PSE applies

two “safe” voltages of less than 10.1V each while

measuring the change in current drawn in order

to determine the load resistance. If the PSE

“sees” the correct load, then it may either further

increase the applied voltage to enter the

“classification” range of operation or switch on

the nominal 48V power to the load.

The classification mode can further specify to the

PSE the expected load range of the device under

power so that the PSE can intelligently distribute

power to as many loads as possible (within its

maximum current capabilities). If a classification

resistance is not present, the PD load is

assumed to be the maximum of approximately 13

Watts. The classification mode is active between

14.5V and 20.5V.

The main power switch will pass a limited current

above 31V, charging the external DC-to-DC

converter’s input capacitor in a controlled manner.

The charging will continue until the controlled

current

drops

below

either

an

externally

programmed limiting level or 450mA, depending

upon the Rlim current setting resistor. The main

power switch is internally thermally protected to

100V by reducing the output current using a

foldback

technique.

The

required

power

dissipation of the IC drops from the allowed peak

The minimum allowed capacitance of 5µF will

charge in 500µs. A larger capacitor will take a

proportionally longer time to charge due to the

constant current charging method. A capacitor

that is too large will overheat the part and force it

into thermal shutdown. The IC will reattempt

charging for a number of cycles but ultimately will

be shut down until the input voltage from the PSE

is recycled. This is the way the IC protects itself

under overload and/or shorted conditions.

Once the capacitor tied between Vdd, Ethernet

input positive supply and the RTN pin is charged

to within a volt of the applied Ethernet input

supply potential, the PG output is driven low to

enable the switching regulator controller. This

delay prior to turning on the switching regulator is

required in order to minimize the power

dissipation incurred during the startup of the

controller. The capacitance tied across the Vdd

and RTN lines provide the inductor ripple current

while maintaining a small voltage differential such

that the average current flowing in the RTN line is

under the current limit level. Without a storage

capacitance at this point, instantaneous current

peaks, required by the switching regulator during

normal operation, would send the main PD

switch (at the RTN pin) in and out of current limit

resulting in high power dissipation due to the

resultant voltage across the “switch”. A current

greater than the current limit value would

increase the voltage on the RTN pin to the

Ehternet

Input

supply

voltage

immediately

resulting in power dissipation levels that would

immediately shut down the PD switch without the

required storage capacitor.

The soft-start capacitor, CSS, slows the rate of

current delivery to the switching regulator to a

value that can be delivered by the storage

capacitor/PD switch.

A resistor tied between the Rdelay pin and

AGND sets a time delay between the falling edge

of the synchronous gate and the rising edge of

the main gate. This delay can be set to

compensate for system delays caused by

architectural structures of the circuit being used.

An isolated secondary type power supply having

a transformer in the feedback loop may require

extra time due to the electrical path incurred. The

delay time is adjustable from as little as 40nSec

to over 200nSec through the choice of resistance

value. A smaller resistance will result in a shorter

delay. Nominal values range from 0 - 200 kΩ for

time delays from 40nSec to 200nSec. The delay