VS6524

2/3

Figure 1. Application Diagram

Figure 2. Block diagram

PART NUMBERING

Table 2. Order Codes

Table 1. Technical Specifications

Active pixels

640H x 480V

Pixel size

3.6 x 3.6µm

Array size

2.38 x 1.77 mm

Color filter array

RGB Bayer

Exposure control

+120 dB

Analog gain

+24 dB (max)

Dynamic range

61 dB (typical)

Signal-to-noise Ratio

35 dB at 100 lux (typical)

Frame rate

1 to 30 Hz

Image format

VGA, QVGA, QQVGA,

subQCIF

Arbitrary cropping

Horizontal/vertical flipping

Pixel format

YUV 4:2:2

RGB 565, RGB 444

Raw Bayer 10-bit

CLK

CE

D[7:0]

VGA Mobile

VS6524

SCL, SDA

Baseband

or

Application

Processor

Camera Module

HSYNC

VSYNC

PCLK

FSO

SCL

SDA

CLK

CE

D[7:0]

HSYNC, VSYNC

PCLK

FSO

AVDD

AGND

VDD

DGND

1152 x 864

640 x 480

Column ADC

X Decoder

Line SRAM

Video

Processor

Camera

Controller

PLL and Clock Management

Power Mgmt

Power-On Reset

Pixel array

VS6524

Video Interface

8-bit parallel video, hsync,

vsync

ITU-R BT.656-4 compliant,

24 MHz max

Clock input

6.5 to 27 MHz square

13 MHz typ. (on-chip PLL)

Supply voltage

2.4 to 3.0 V analog

I/O voltage

1.8 or 2.8 V +/- 0.1 V

CMOS levels

Power consumption

Streaming 30 fps: 30 mA

max

Power down: 10 µA max.

Lens

2-element, 50° HFOV, F#

2.8

Depth of field

20 cm to infinite

TV distortion

< 1%

Relative illumination

45% typ.

Package type

SmOP2

Package size

7.0 x 7.0 x 4.5 mm (wlh)

System attach

FPC with 20-pin B2B

connector, Molex 55560-

a.

Contact us for custom FPC designs and/or ZIF connector

variants

Part Number

Description

VS6524P02S

SmOP2 7.0 x 7.0 x 4.5 mm

FPC attach, tray packing

Table 1. Technical Specifications