ADL5604ACPZ-R7 datasheet(19/23 Pages) AD

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Data Sheet

ADL5604

Rev. C | Page 19 of 23

ACPR AND EVM

All adjacent channel power ratio (ACPR) and error vector

magnitude (EVM) measurements were made using a single

W-CDMA carrier and Test Model 1-64.

The signal is generated by a very low ACPR source and is

measured at the output by a high dynamic range spectrum

analyzer. For ACPR measurements, the filter setting was chosen

for low ACPR and for EVM measurements the low EVM setting

was selected. The baseline composite EVM for the signal source

used was around 0.5%. Highly linear amplifiers were used to

measure ACPR and EVM at higher output power levels.

Figure 26 shows the plot of ACPR vs. POUT at 946 MHz. Shown

on the same plot is the system ACPR. For power levels up to

11 dBm, an ACPR of 65 dBc or better can be achieved.

Figure 27 shows the ACPR vs. POUT at 1966 MHz. Shown on

the same plot is the system ACPR. For power levels up to 11 dBm,

an ACPR of 65 dBc or better can be achieved.

Figure 28 shows ACPR vs. POUT at 2140 MHz. Shown on the

same plot is the system ACPR. For power levels up to 12 dBm,

an ACPR of 65 dBc or better can be achieved. Figure 29 shows

the plot of EVM vs. POUT at 946 MHz. The EVM measured is

less than 1% for power levels up to 15 dBm.

Figure 30 shows the EVM vs. POUT at 1966 MHz. The EVM

measured is less than 1% for power levels up to 18 dBm.

Figure 31 shows the EVM vs. POUT at 2140 MHz. The EVM

measured is less than 1% for power levels up to 18 dBm.

When operated in the linear region, there is little or no

contribution to EVM by the amplifier.

THERMAL CONSIDERATIONS

The ADL5604 is packaged in a thermally efficient 4 mm × 4 mm,

16-lead LFCSP. The thermal resistance from junction to air (θJA)

is 32.1oC/W. The thermal resistance for the product was extracted

assuming a standard 4-layer JEDEC board with nine copper

filled thermal vias. The thermal resistance from junction to case

(θJC) is 6°C/W where case is the exposed pad of the lead frame

package.

For the best thermal performance, it is recommended to add as

many thermal vias as possible under the exposed pad of the

LFCSP. The above thermal resistance numbers assume a

minimum of nine thermal vias arranged in a 3 × 3 array with a

diameter of 8 mils and a pitch of 16 mils. Because the top and

bottom leads of the package are ground, the ground pattern on

the evaluation board is extended on the top and bottom to

improve thermal efficiency (see the Evaluation Board section).

SOLDERING INFORMATION AND RECOMMENDED

PCB LAND PATTERN

Figure 43 shows the recommended land pattern for the ADL5604.

To minimize thermal impedance, the exposed paddle on the

4 mm × 4 mm LFCSP package is soldered down to a ground

plane along with Pin 5 to Pin 8 and Pin 13 to Pin 16. To improve

thermal dissipation, nine thermal vias are arranged in a 3 × 3

array under the exposed paddle. Areas above and below the

paddle are tied with regular vias. If multiple ground layers exist,

they should be tied together using vias. For more information on

land pattern design and layout, see the AN-772 Application

Note, A Design and Manufacturing Guide for the Lead Frame

Chip Scale Package (LFCSP).

RFIN

RFOUT

THERMAL VIAS

8 MIL

FILLED VIAs

16 MIL

FILLED VIAs

Figure 43. Recommended Land Pattern

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