MP3331-2A SYNCHRONOUS BOOST FLASH LED DRIVER WITH I

MP3331 Rev. 1.02

www.MonolithicPower.com

15

5/3/2016

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© 2016 MPS. All Rights Reserved.

Figure 11: 5V DC Mode

Switching Frequency Setting

The switching frequency is selected by SW_FS

bits. 1M/2M/3M/4MHz are available to optimize

efficiency.

Switching Frequency Foldback

In default 4MHz switching mode, if the voltage

across the current source is larger than the

value set by the register bits VTH_PAS, the IC

switches to 1MHz mode to improve efficiency

and EMI. In 1MHz mode, the switching

frequency can be stretched down according to

the load condition with FS_SD =0. The IC goes

into

pass

mode

(which

turns

on

the

synchronous PMOS fully) if the input voltage is

high enough.

Current Reduction

When the MP3331 works in flash mode, output

current reduction may occur due to the

following conditions:

1. TX is high.

During flash mode, if TOR/TX goes from low to

high, the flash current drops to the current set

by I_TX in less than 5µs and sets the FT_TX bit

to 1. If TX goes low, the current ramps up to the

flash current again (see Figure 12).

Figure 12: Flash Mode when TX is Active

2. Low

battery

voltage

threshold

is

triggered

.

During a flash pulse, if the battery voltage drops

below the threshold set by VBL_RUN, the

current reduces step-by-step with a 2µs/step

until the battery voltage rises up to the specific

low battery voltage threshold. Actual current in

the IFL_ACT register can be read back. The

minimum current caused by the current

reduction in IFL_MIN can be read back after the

flash.

Low Battery Voltage Protection

The device provides low battery voltage

protection in flash mode in the following ways:

1. Before the flash, if the input voltage is lower

than the threshold set by VBL_RUN, the device

remains disabled (if VBL_SD = 1 and sets the

fault bit FT_VBATL to 1). If VBL_SD = 0, the

device ramps to the current set by I_TX and

sets the fault bit FT_VBATL to 1. The fault bit is

cleared after read back or the input power

resets.

2. During flash start-up, if the input voltage is

lower than the threshold set by VBL_RUN, the

current stops ramping. The fault bit FT_VBATL

is set. During the flash pulse, if the input voltage

is lower than the threshold set by VBL_RUN,

the current ramps down step-by-step. The fault

bit is set until read back or the input power

resets. After the flash, the minimum current

caused by the current reduction is read back

through the IFL_MIN register. The IFL_MIN

value holds until the next flash occurs or the

power resets. The actual current is read back

through IFL_ACT during flash time. This