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MP3336 数据表(PDF) 15 Page - Monolithic Power Systems |
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MP3336 数据表(HTML) 15 Page - Monolithic Power Systems |
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15 / 27 page ![]() MP3336 – DUAL-CHANNEL, FLASH LED DRIVER WITH I 2C INTERFACE MP3336 Rev.1.01 www.MonolithicPower.com 15 5/16/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. Switching Frequency Fold-back When the max switching frequency is set to 2/3/4MHz in switching mode, if the voltage across the current source is larger than the value set by the register bits VTH_PAS, the IC switches to 1MHz to improve efficiency and EMI. With 1MHz, if the voltage across the current source is still larger than the value set by the register bits VTH_PAS, the IC can stretch the frequency down until it reaches about 100kHz with FS_SD = 0. If the LED load becomes lighter and the input voltage increases further, the IC switches to pass mode from 100kHz. With FS_SD = 1, the IC switches directly to pass mode from 1MHz. Load Balancing To improve efficiency, the device provides load balancing to prevent unbalanced forward voltage drops between the dual LEDs (see Figure 13). To enable this function, the bit BAL_ON must be set to 1. Supposing VLED1 > VLED2 + VLED_HYS, the LED1 current drops step by step while the LED2 current rises step by step. Finally, |VLED1 - VLED2| < VLED_HYS or ILED1 < 90%ILED2. However, the maximum adjustment range of each LED current is limited to 10%. Because of the limitation, if there is a large difference between VLED1 and VLED2, the load balance function cannot make |VLED1 - VLED2| drop below VLED_HYS, but it is still helpful to further reduce the voltage difference and improve efficiency. Conversely, if VLED2 > VLED1 + VLED_HYS, the operation is the same. Figure 13: Load Balancing LED Output Current Reduction When the MP3336 works in flash mode, output current reduction may occur due to the following three conditions: 1. TX is High During flash mode, if TX goes from low to high, the flash current drops to the current set by I_TX in under 5µs and sets the FT_TX bit to 1. If TX goes low, the current ramps up to the flash current again (see Figure 14). Figure 14: Flash Mode with TX Pulse 2. Input DC Current Limit is Triggered If the input DC current limit set by IL_DC register is not sufficient, a current reduction may occur. The actual current in the IFL_ACT register can be read back during flash. Input DC Current Limit Protection The MP3336 uses the input DC current limit protection to avoid drawing too much current from the battery. This current limit can be programmed by the IL_DC register from 1A to 4.2A with 250mA/step when IL_DC < 3A and with 300mA/step when IL_DC > 3A. If the input current hits the input current limit threshold, the LED output current stops and holds until the input current limit drops below the current limit threshold. The fault bit FT_IDC is set to 1 if the input current limit is triggered. The fault bit remains until it is read back or the input power is reset. The input current limit protection is useful in boost mode because it senses the current of the low-side MOSFET. |
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