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MP3398A 数据表(PDF) 16 Page - Monolithic Power Systems |
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MP3398A 数据表(HTML) 16 Page - Monolithic Power Systems |
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16 / 20 page ![]() STEP UP, 4 STRINGS, MAX. 350MA/STRING ANALOG AND PWM DIMMING, WHITE LED CONTROLLER MP3398A Rev. 1.04 www.MonolithicPower.com 16 5/26/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2017 MPS. All Rights Reserved. amplitude of the PWM signal is 1.5V and the low level should be less than 0.4V. Table 1 —The Range of PWM Dimming Duty fPWM(Hz) Dmin Dmax 100<f 200 0.30% 100% 200<f 500 0.75% 100% 500<f 1k 1.50% 100% 1k<f 2k 3.00% 100% 2k<f 5k 7.50% 100% 5k<f 10k 15.00% 100% 10k<f 20k 30.00% 100% 2. Analog Dimming For analog dimming, apply a PWM signal or a DC voltage signal to ADIM pin. An internal RC filter (10Mohm resistor and 100pF capacitor) is integrated to this pin. So, if a PWM signal applied to this pin, >20kHz frequency is recommended to get a better PWM signal filtering performance and make sure the amplitude voltage is higher than 1.5V and low level voltage is less than 0.4V with >15mV/ns slope rate for falling/rising edge. For DC signal input, please apply a DC input signal range from 0.4V to 1.5V to linearly set the LED current from 0% to 100%. Expanding LED Channels The MP3398A can expand the number of LED channels by using two or three MP3398A in parallel. To connect two MP3398A for a total of 8 LED strings, tie the VCC pins of the master IC and the slave IC together to power the slave IC internal logic circuitry. Tie the COMP pins of the slave IC and the master IC together to regulate the voltage of all 8 strings LEDs. The slave IC MOSFET driving signals are not used; the boost converter can be only driven by the master IC. Do not leave the ISENSE pin of the slave IC floating; tie it to ground. Apply the EN and DIM signals to both ICs. Layout Considerations The circuit layout for the MP3398A requires special attention to reduce EMI noise. The loop from the external MOSFET (M1), through the output diode (D1) and the output capacitor (C2, C3) carry a high-frequency pulse current and must be as small and short as possible (See Figure 3). Figure 3 —Layout Consideration All logic signals refer to the signal ground. in order to reduce the noise affection, it is recommend to separate the power ground(PGND) and signal ground(GND), then connect PGND and GND together. |
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