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MP2145GD 数据表(PDF) 8 Page - Monolithic Power Systems

部件名 MP2145GD
功能描述  5.5V, 6A, 1.2MHz, High-Efficiency, 40uA IQ Constant On-Time Synchronous, Step-Down Switcher Evaluation Board
PDF  8 Pages
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制造商  MPS [Monolithic Power Systems]
网页  http://www.monolithicpower.com
标志 MPS - Monolithic Power Systems

MP2145GD 数据表(HTML) 8 Page - Monolithic Power Systems

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EV2145-D-00A – 6A, 5.5V, 1.2MHZ, SYNC STEP-DOWN SWITCHER
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
EV2145-D-00A Rev.1.0
www.MonolithicPower.com
8
8/14/2014
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
QUICK START GUIDE
1. Connect the positive and negative terminals of the load to the VOUT and GND pins,
respectively.
2. Preset the power supply output between 2.8V and 5.5V, and then turn off the power supply.
3. Connect the positive and negative terminals of the power supply output to the VIN and GND
pins, respectively.
4. Turn the power supply on. The board will automatically start up.
5. To use the Enable function, apply a digital input to the EN pin. Drive EN higher than 1.2V to turn
on the regulator or less than 0.4V to turn it off.
LAYOUT RECOMMENDATION OF MP2145
Proper layout of the switching power supplies is very important, and sometimes critical to make it work
properly. Especially, for the high switching converter, if the layout is not carefully done, the regulator
could show poor line or load regulation, stability issues.
For MP2145, the high speed step-down regulator, the input capacitor should be placed as close as
possible to the IC pins. As shown in Figure 6, the 0805 size ceramic capacitor is used, please make
sure the two ends of the ceramic capacitor be directly connected to PIN 8 (the Power Input Pin) and
PIN 10/11/12 (the Power GND Pin).
1
4
10
9
37
6
12
SW
OUT
RAMP
FB
VIN
SW
VIN
PG
EN
MODE/
VCON
GND GNDGND
5
28
11
Cin
Cout
R1
R2
GND
Pin10,11,12
(PGND )
Pin8
(VIN )
Lout
Figure 6— Two ends of Input decoupling Capacitor close to Pin 8 and Pin 10/11/12



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