1/10

April 2001

s

s

LOW POWER DISSIPATION:

s

COMPATIBLE WITH TTL OUTPUTS

s

50

Ω TRANSMISSION LINE DRIVING

CAPABILITY

s

SYMMETRICAL OUTPUT IMPEDANCE:

s

BALANCED PROPAGATION DELAYS:

s

OPERATING VOLTAGE RANGE:

s

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

s

IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74ACT138 is an advanced high-speed CMOS

3 TO 8 LINE DECODER (INVERTING) fabricated

with sub-micron silicon gate and double-layer

If the device is enabled, 3 binary select inputs (A,

B, and C) determine which one of the outputs will

go low. If enable input G1 is held low or either G2A

or G2B is held high, the decoding function is

inhibited and all the 8 outputs go to high.

Three enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

The device is designed to interface directly High

Speed CMOS systems with TTL, NMOS and

CMOS output voltage levels.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74ACT138

3 TO 8 LINE DECODER (INVERTING)

PIN CONNECTION AND IEC LOGIC SYMBOLS

ORDER CODES

PACKAGE

TUBE

T & R

DIP

74ACT138B

SOP

74ACT138M

74ACT138MTR

TSSOP

74ACT138TTR

TSSOP

DIP

SOP