AT45DB321C datasheet(2/37 Pages) ATMEL

2 / 37 page

AT45DB321C [Preliminary]

3387B–DFLSH–9/04

Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addi-

tion to the 33-megabit main memory, the AT45DB321C also contains two SRAM

buffers of 528 bytes each.

The buffers allow the receiving of data while a page in the main page Memory is being

reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit or

byte alterability) is easily handled with a self-contained three step read-modify-write

operation. Unlike conventional Flash memories that are accessed randomly with multi-

ple address lines and a parallel interface, the DataFlash uses a RapidS serial interface

to sequentially access its data. The simple sequential access dramatically reduces

active pin count, facilitates hardware layout, increases system reliability, minimizes

switching noise, and reduces package size. The device is optimized for use in many

commercial and industrial applications where high-density, low-pin count, low-voltage

and low-power are essential. The device operates at clock frequencies up to 40 MHz

with a typical active read current consumption of 10 mA.

To allow for simple in-system reprogrammability, the AT45DB321C does not require

high input voltages for programming. The device operates from a single power supply,

2.7V to 3.6V, for both the program and read operations. The AT45DB321C is enabled

through the chip select pin (CS) and accessed via a three-wire interface consisting of

the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).

All programming and erase cycles are self-timed.

Block Diagram

Memory Array

To provide optimal flexibility, the memory array of the AT45DB321C is divided into three

levels of granularity comprising of sectors, blocks, and pages. The “Memory Architec-

ture Diagram” illustrates the breakdown of each level and details the number of pages

per sector and block. All program operations to the DataFlash occur on a page by page

basis. The erase operations can be performed at the block or page level.

FLASH MEMORY ARRAY

PAGE (528 BYTES)

BUFFER 2 (528 BYTES)

BUFFER 1 (528 BYTES)

I/O INTERFACE

SCK

RESET

VCC

GND

RDY/BUSY

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