Block Diagram

20085902

Device Operation

BLOCK DESCRIPTION

The Equalizer block is a multi-stage adaptive filter. If Bypass

is high, the equalizer is disabled.

The DC Restore block receives the differential signals from

the equalizer filter block. This block incorporates a self-

biasing DC restore circuit to fully DC restore the signals. If

Bypass is high, this function is disabled.

The Output block produces SDO and SDO.

The Cable Length Indicator provides a voltage to indicate

the length of cable being equalized.

The Mute Reference determines the amount of cable to

equalize before muting the outputs. This is set by applying a

voltage proportional to the required length of cable. The

higher the voltage, the lower the mute threshold.

Carrier Detect / Mute is bi-directional, serving two pur-

poses. As an output, carrier detect monitors the signal power

out of the equalizing filter and compares it to the mute

reference to determine if a valid signal is present. Carrier

detect provides a high voltage when no signal is present.

Mute can be forced on or off by using this pin as an input.

Mute is forced off if this pin is tied to ground, and the outputs

will always mute if this pin is tied to V

The loop response in the AEC block is controlled by an

external 1µF capacitor placed across the AEC+ and AEC-

pins.

INPUT INTERFACING

The CLC034 accepts either differential or single-ended in-

put. The input must be AC coupled. Transformer coupling is

not supported.

The CLC034 correctly handles equalizer pathological signals

for standard definition and high definition serial digital video,

as described in SMPTE RP 178 and RP 198, respectively.

OUTPUT INTERFACING

The SDO and SDO outputs are internally loaded with 50

Ω.

They produce a 750 mV

P-P

differential output, or a

375 mV

REPLACING THE GENNUM GS1524

The CLC034 is form-fit-function compatible with the Gennum

GS1524.

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