LT3790 datasheet(21/32 Pages) LINER

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LT8390

8390fa

For more information www.linear.com/LT8390

APPLICATIONS INFORMATION

From a known power dissipated in the power MOSFET, its

junction temperature can be obtained using the following

formula:

TJ = TA + P • RTH(JA)

The junction-to-ambient thermal resistance RTH(JA) in-

cludes the junction-to-case thermal resistance RTH(JC)

and the case-to-ambient thermal resistance RTH(CA). This

value of TJ can then be compared to the original, assumed

value used in the iterative calculation process.

Optional Schottky Diode (DB, DD) Selection

The optional Schottky diodes DB (in parallel with switch

B) and DD (in parallel with switch D) conduct during the

dead time between the conduction of the power MOSFET

switches. They are intended to prevent the body diode of

synchronousswitchesBandDfromturningonandstoring

charge during the dead time. In particular, DB significantly

reduces reverse recovery current between switch B turn-

off and switch A turn-on, and DD significantly reduces

reverse recovery current between switch D turn-off and

switch C turn-on. They improve converter efficiency and

reduce switch voltage stress. In order for the diode to be

effective, the inductance between it and the synchronous

switch must be as small as possible, mandating that these

components be placed adjacently.

CIN and COUT Selection

Input and output capacitance is necessary to suppress

voltage ripple caused by discontinuous current moving

in and out the regulator. A parallel combination of capaci-

tors is typically used to achieve high capacitance and low

equivalent series resistance (ESR). Dry tantalum, special

polymer,aluminumelectrolyticandceramiccapacitorsare

all available in surface mount packages. Capacitors with

low ESR and high ripple current ratings, such as OS-CON

and POSCAP are also available.

Ceramic capacitors should be placed near the regula-tor

input and output to suppress high frequency switching

spikes. Ceramic capacitors, of at least 1µF, should also

be placed from VIN to GND and VOUT to GND as close to

the LT8390 pins as possible. Due to their excellent low

ESR characteristics, ceramic capacitors can significantly

reduce input ripple voltage and help reduce power loss in

the higher ESR bulk capacitors. X5R or X7R dielectrics are

preferred, as these materials retain their capacitance over

wide voltage and temperature ranges. Many ceramic ca-

pacitors,particularly0805or0603casesizes,havegreatly

reduced capacitance at the desired operating voltage.

Input Capacitance CIN: Discontinuous input current is

highest in the buck region due to the switch A toggling

on and off. Make sure that the CIN capacitor network has

low enough ESR and is sized to handle the maximum RMS

current. In buck region, the input RMS current is given by:

IRMS ≈ IOUT(MAX) •

VOUT

VIN

•

VIN

VOUT

−1

The formula has a maximum at VIN = 2VOUT, where IRMS

= IOUT(MAX)/2. This simple worst-case condition is com-

monly used for design because even significant deviations

do not offer much relief.

Output Capacitance COUT: Discontinuous current shifts

from the input to the output in the boost region. Make sure

that the COUT capacitor network is capable of reducing

the output voltage ripple. The effects of ESR and the bulk

capacitance must be considered when choosing the right

capacitor for a given output ripple voltage. The maximum

steady state ripple due to charging and discharging the

bulk capacitance is given by:

∆VCAP(BOOST) =

IOUT(MAX) • VOUT − VIN(MIN)

(

)

COUT • VOUT • f

∆VCAP(BUCK) =

VOUT • 1−

VOUT

VIN(MAX)













8 •L • f2 • COUT

The maximum steady ripple due to the voltage drop across

the ESR is given by:

∆VESR(BOOST) =

VOUT •IOUT(MAX)

VIN(MIN)

•ESR

∆VESR(BUCK) =

VOUT • 1−

VOUT

VIN(MAX)













L • f

•ESR

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