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LT8705 数据表(PDF) 13 Page - Linear Technology |
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LT8705 数据表(HTML) 13 Page - Linear Technology |
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13 / 38 page ![]() LTC3784 13 3784fb For more information www.linear.com/LTC3784 operaTion the PLL loop only needs to make slight changes to the VCO input in order to synchronize the rising edge of the external clock’s to the rising edge of BG1. The ability to prebias the loop filter allows the PLL to lock-in rapidly without deviating far from the desired frequency. The typical capture range of the LTC3784’s PLL is from approximately 55kHz to 1MHz, and is guaranteed to lock to an external clock source whose frequency is between 75kHz and 850kHz. The typical input clock thresholds on the PLLIN/MODE pin are 1.6V (rising) and 1.2V (falling). The recommended maximumamplitudeforlowlevelandminimumamplitude forhighlevelofexternalclockare0Vand2.5V,respectively. PolyPhase Applications (CLKOUT and PHASMD Pins) The LTC3784 features two pins, CLKOUT and PHASMD, that allow other controller ICs to be daisy-chained with the LTC3784 in PolyPhase applications. The clock output signal on the CLKOUT pin can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or multiple separate outputs. The PHASMD pin is used to adjust the phase of the CLKOUT signal as well as the relative phases between the two internal controllers, as summarized in Table 1. The phases are calculated relative to the zero degrees phase being defined as the rising edge of the bottom gate driver output of controller 1 (BG1). Depend- ing on the phase selection, a PolyPhase application with multiple LTC3784s can be configured for 2-, 3-, 4- , 6- and 12-phase operation. Table 1. VPHASMD CONTROLLER 2 PHASE (°) CLKOUT PHASE (°) GND 180 60 Floating 180 90 INTVCC 240 120 CLKOUT is disabled when the controller is in shutdown or in sleep mode. Operation When VIN > Regulated VOUT WhenVINrisesabovetheregulatedVOUTvoltage,theboost controller can behave differently depending on the mode, inductor current and VIN voltage. In forced continuous mode, the control loop works to keep the top MOSFET on continuouslyonceVINrisesaboveVOUT.Theinternalcharge pump delivers current to the boost capacitor to maintain a sufficiently high TG voltage. The amount of current the charge pump can deliver is characterized by two curves in the Typical Performance Characteristics section. In pulse-skipping mode, if VIN is between 100% and 110% of the regulated VOUT voltage, TG turns on if the inductor current rises above a certain threshold and turns off if the inductor current falls below this threshold. This threshold current is set to approximately 6%, 4% or 3% of the maximum ILIM current when the ILIM pin is grounded, floating or tied to INTVCC, respectively. If the controller is programmed to Burst Mode operation under this same VIN window, then TG remains off regardless of the inductor current. If the OVMODE pin is grounded and VIN rises above 110% of the regulated VOUT voltage in any mode, the controller turns on TG regardless of the inductor current. In Burst Mode operation, however, the internal charge pump turns off if the chip is asleep. With the charge pump off, there would be nothing to prevent the boost capacitor from discharging, resulting in an insufficient TG voltage needed to keep the top MOSFET completely on. To prevent exces- sive power dissipation across the body diode of the top MOSFET in this situation, the chip can be switched over to forced continuous mode to enable the charge pump; a Schottky diode can also be placed in parallel with the top MOSFET. Power Good The PGOOD pin is connected to an open drain of an internal N-channel MOSFET. The MOSFET turns on and pulls the PGOOD pin low when the VFB pin voltage is not within ±10% of the 1.2V reference voltage. The PGOOD pin is also pulled low when the corresponding RUN pin is low (shut down). When the VFB pin voltage is within the ±10% requirement, the MOSFET is turned off and the pin is allowed to be pulled up by an external resistor to a source of up to 6V (abs max). |
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