L6911D

10/17

The worst condition depends on the input voltage available and the output voltage selected. Anyway the worst

case is the response time after removal of the load with the minimum output voltage programmed and the max-

imum input voltage available.

Output Capacitor

Since the microprocessors require a current variation beyond 10A doing load transients, with a slope in the

range of tenth A/

µsec, the output capacitor is a basic component for the fast response of the power supply. In

fact for first few microseconds they supply the current to the load. The controller recognizes immediately the

load transient and sets the duty cycle at 100%, but the current slope is limited by the inductor value.

The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the

ESL):

A minimum capacitor value is required to sustain the current during the load transient without discharge it. The

voltage drop due to the output capacitor discharge is given by the following equation:

during load transient and the lower is the output voltage static ripple.

Input Capacitor

The input capacitor has to sustain the ripple current produced during the on time of the upper MOS, so it must

have a low ESR to minimize the losses. The rms value of this ripple is:

Where D is the duty cycle. The equation reaches its maximum value with D=0.5. The losses in worst case are:

Compensation network design

The control loop is a voltage mode (figure 7) that uses a droop function to satisfy the requirements for a VRM

module, reducing the size and the cost of the output capacitor.

This method "recovers" part of the drop due to the output capacitor ESR in the load transient, introducing a de-

pendence of the output voltage on the load current: at light load the output voltage will be higher than the nom-

inal level, while at high load the output voltage will be lower than the nominal value.

t

a pplic atio n

L

∆I

⋅

V

IN

V

OUT

–

------------------------------

=

t

rem ov al

L

∆I

⋅

V

OUT

---------------

=

∆V

OUT

∆I

OUT

2

L

2C

OU T

V

IN M IN

D

MAX

V

OUT

–

⋅

()

⋅⋅

---------------------------------------------------------------------------------------------

=

I

rm s

I

OUT

D1

D

–

()

⋅

=

P

ESR I

rm s

2

⋅

=