LTC2000A

39

2000afb

For more information www.linear.com/LTC2000A

APPLICATIONS INFORMATION

0.4 cycles, the DCKIP/N rising edges are arriving in dif-

ferent sample clock cycles.

For the example in Figure 15a, we might read 0x25 for

SYNC_PH on DAC X and 0x52 on DAC Y. Table 12 tells us

that the DCKIP/N to CKP/N delay is greater than 0.8 cycles

for DAC X and less than 0.2 cycles for DAC Y, and thus the

differencebetweenthemisatleast0.6cycles. Weconclude

that the DCKIP/N rising edge of DAC X must fall within

a later sample clock cycle than that of DAC Y, and thus

that DAC X is being updated one cycle later than DAC Y.

To correct any such misalignment and synchronize the

DACs, consult Table 12 and adjust the SYNC_PS settings

for those DACs which are being updated one cycle late

(DAC X in the above example) by setting the synchronizer

to manual mode (SYNC_MSYN = 1) and overwriting the

SYNC_PS value.

In this example, reading register 0x06 of DAC X shows

SYNC_PH = 0x25 and that the SYNC_PS setting needs to

change from the default (10) to the desired adjusted value

(00),subtractingonecyclefromthelatencyofDACX(refer

to Table 12). Write 0x04 to register 0x05 of DAC X to set

SYNC_MSYN = 1 and SYNC_PS = 00. The outputs of DAC

X should now align with DAC Y as shown in Figure 15a.

SeeTable6fordetailsregardingthesynchronizerregisters

0x05 and 0x06. Sample verilog code implementing the

synchronization of multiple LTC2000As using Tables 12

and 13 can be found at:

http://www.linear.com/docs/44845

Synchronizing Multiple LTC2000As in Single-Port Mode

Figure15bshowssamplewaveformsforsynchronizingtwo

LTC2000As in single port mode. Synchronizing multiple

LTC2000As in single port mode is essentially the same

Table 12. Adjusting Latency in Dual-Port Mode

PHASE COMPARATOR OUTPUTS

SYNC_PH (REG 0x06)

DELAY FROM DCKIP/N RISING

EDGE TO NEXT CKP/N RISING EDGE

(CKP/N CYCLES)

SYNC_PS SETTING

(DEFAULT)

(ADJUSTED TO REDUCE LATENCY

BY 1 CYCLE)*

0x03

0 to 0.2

10

N/A

0x04

0.2 to 0.4

10

N/A

0x05

0.4 to 0.6

10

N/A

0x15

0.6 to 0.8

10

00

0x25

0.8 to 1.0

10

00

0x35

0 to 0.2

00

N/A

0x45

0.2 to 0.4

00

N/A

0x55

0.4 to 0.6

00

N/A

0x54

0.6 to 0.8

00

01

0x53

0.8 to 1.0

00

01

0x52

0 to 0.2

01

N/A

0x51

0.2 to 0.4

01

N/A

0x50

0.4 to 0.6

01

N/A

0x40

0.6 to 0.8

01

11

0x30

0.8 to 1.0

01

11

0x20

0 to 0.2

11

N/A

0x10

0.2 to 0.4

11

N/A

0x00

0.4 to 0.6

11

N/A

0x01

0.6 to 0.8

11

10

0x02

0.8 to 1.0

11

10

*N/A indicate SYNC_PH values that should not occur if the timing mismatch requirements described above are met. If such a case occurs,

keep SYNC_PS as the default value.