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LTC2611CDD 数据表(PDF) 2 Page - Linear Technology

部件名 LTC2611CDD
功能描述  16-/14-/12-Bit Rail-to-Rail DACs in 10-Lead DFN
PDF  16 Pages
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC2611CDD 数据表(HTML) 2 Page - Linear Technology

  LTC2611CDD Datasheet HTML 1Page - Linear Technology LTC2611CDD Datasheet HTML 2Page - Linear Technology LTC2611CDD Datasheet HTML 3Page - Linear Technology LTC2611CDD Datasheet HTML 4Page - Linear Technology LTC2611CDD Datasheet HTML 5Page - Linear Technology LTC2611CDD Datasheet HTML 6Page - Linear Technology LTC2611CDD Datasheet HTML 7Page - Linear Technology LTC2611CDD Datasheet HTML 8Page - Linear Technology LTC2611CDD Datasheet HTML 9Page - Linear Technology Next Button
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LTC2601/LTC2611/LTC2621
2601f
A
G
A
U
A
R
BSOLUTEXI
TI
S
ORDER PART
NUMBER
PACKAGE/ORDER I FOR ATIO
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND
MUST BE SOLDERED TO PCB
(Note 1)
Any Pin to GND ........................................... – 0.3V to 6V
Any Pin to VCC .............................................– 6V to 0.3V
Maximum Junction Temperature ......................... 125
°C
Operating Temperature Range
LTC2601C/LTC2611C/LTC2621C .......... 0
°C to 70°C
LTC2601I/LTC2611I/LTC2621I .......... – 40
°C to 85°C
Storage Temperature Range ................ – 65
°C to 125°C
Lead Temperature (Soldering, 10 sec)................ 300
°C
DD PART MARKING
ELECTRICAL C
C
HARA TERISTICS The q denotes specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. REF = 4.096V (VCC = 5V), REF = 2.048V (VCC = 2.5V), VOUT unloaded,
unless otherwise noted.
LTC2601CDD
LTC2601IDD
LTC2611CDD
LTC2611IDD
LTC2621CDD
LTC2621IDD
LAGT
LBFQ
LBFS
Consult LTC Marketing for parts specified with wider operating temperature ranges.
TOP VIEW
11
DD PACKAGE
10-LEAD (3mm
× 3mm) PLASTIC DFN
10
9
6
7
8
4
5
3
2
1
LDAC
VCC
GND
VOUT
REF
SDO
SDI
SCK
CLR
CS/LD
LTC2621
LTC2611
LTC2601
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
DC Performance
Resolution
q
12
14
16
Bits
Monotonicity
(Note 2)
q
12
14
16
Bits
DNL
Differential Nonlinearity
(Note 2)
q
±0.5
±1
±1
LSB
INL
Integral Nonlinearity
(Note 2)
q
±0.8 ±4
±3
±16
±13 ±64
LSB
Load Regulation
VREF = VCC = 5V, Midscale
IOUT = 0mA to 15mA Sourcing
q
0.03 0.125
0.10
0.5
0.45
2
LSB/mA
IOUT = 0mA to 15mA Sinking
q
0.04 0.125
0.15
0.5
0.60
2
LSB/mA
VREF = VCC = 2.5V, Midscale
IOUT = 0mA to 7.5mA Sourcing
q
0.06
0.25
0.2
1
0.9
4
LSB/mA
IOUT = 0mA to 7.5mA Sinking
q
0.08
0.25
0.3
1
1.2
4
LSB/mA
ZSE
Zero-Scale Error
Code = 0
q
19
19
19
mV
VOS
Offset Error
(Note 5)
q
±1.5 ±9
±1.5 ±9
±1.5 ±9mV
VOS Temperature
±5
±5
±5
µV/°C
Coefficient
GE
Gain Error
q
±0.03 ±0.7
±0.1 ±0.7
±0.05 ±0.7
%FSR
Gain Temperature
±2
±2
±2
ppm/
°C
Coefficient



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