LTC6253-7

13

62537f

For more information www.linear.com/LTC6253-7

APPLICATIONS INFORMATION

Input Offset Voltage

The offset voltage will change depending upon which

input stage is active. The PNP input stage is active from

the negative supply rail to approximately 1.2V below the

positive supply rail, then the NPN input stage is activated

for the remaining input range up to the positive supply rail

with the PNP stage inactive. The offset voltage magnitude

for the PNP input stage is trimmed to less than 350µV with

5V total supply at room temperature, and is typically less

than 150μV. The offset voltage for the NPN input stage is

less than 2.2mV with 5V total supply at room temperature.

Input Bias Current

The LTC6253-7 uses a bias current cancellation circuit

to compensate for the base current of the PNP input pair.

put common mode voltage is less than 200mV, the bias

cancellation circuit is no longer effective and the input

bias current magnitude can reach a value above 4µA. For

common mode voltages ranging from 0.2V above the

negative supply to 1.2V below the positive supply, the

low input bias current allows the amplifiers to be used in

applications with high source resistances where errors

due to voltage drops must be minimized.

Output

The LTC6253-7 has excellent output drive capability. The

amplifiers can typically deliver 90mA of output drive cur-

rent at a total supply of 5V. The maximum output current

is a function of the total supply voltage. As the supply

voltage to the amplifier decreases, the output current

capability also decreases. Attention must be paid to keep

the junction temperature of the IC below 150°C (refer

to the Power Dissipation Section) when the output is in

continuous short-circuit. The output of the amplifier has

reverse-biased diodes connected to each supply. If the

output is forced beyond either supply, extremely high

current will flow through these diodes which can result

in damage to the device. Forcing the output to even 1V

beyond either supply could result in several hundred mil-

liamps of current through either diode.

Input Protection

TheLTC6253-7’sinputstagesareprotectedagainstalarge

differential input voltage of 1.4V or higher by 2 pairs of

back-to-back diodes to prevent the emitter-base break-

down of the input transistors. In addition, the input and

shutdown pins have reverse biased diodes connected to

the supplies. The current in these diodes must be limited

to less than 10mA. The amplifiers should not be used as

comparators or in other open loop applications.

ESD

The LTC6253-7 has reverse-biased ESD protection diodes

on all inputs and outputs as shown in Figure 1.

There is an additional clamp between the positive and

negative supplies that further protects the device during

ESD strikes. Hot plugging of the device into a powered

socket must be avoided since this can trigger the clamp

resultinginlargercurrentsflowingbetweenthesupplypins.

Capacitive Loads

The LTC6253-7 has been optimized for speed and should

not be used to drive large capacitors without resistive

isolation. Increased capacitance at the output creates an

additionalpoleintheopenloopfrequencyresponse,wors-

ening the phase margin. When driving capacitive loads, a

resistor of 10Ω to 100Ω should be connected between the

amplifier output and the capacitive load to avoid ringing

or oscillation. The feedback should be taken directly from

the amplifier output. Higher voltage gain configurations

tend to have better capacitive drive capability than lower

gain configurations due to lower closed loop bandwidth

and hence higher phase margin. The graphs titled Series

Output Resistor vs Capacitive Load demonstrate the tran-

sient response of the amplifier when driving capacitive

loads with various series resistors.