PIC18C Reference Manual

DS39504A-page 4-2

 2000 Microchip Technology Inc.

4.1

Introduction

The high performance of the PIC18CXXX devices can be attributed to a number of architectural

features commonly found in RISC microprocessors. These include:

• Harvard architecture

• Long Word Instructions

• Single Word Instructions

• Single Cycle Instructions

• Instruction Pipelining

• Reduced Instruction Set

• Register File Architecture

• Orthogonal (Symmetric) Instructions

Figure 4-2 shows a general block diagram for PIC18CXXX devices.

Harvard Architecture:

Harvard architecture has the program memory and data memory as separate memories which

are accessed from separate buses. This improves bandwidth over traditional von Neumann

architecture in which program and data are fetched from the same memory using the same bus.

To execute an instruction, a von Neumann machine must make one or more (generally more)

accesses across the 8-bit bus to fetch the instruction. Then data may need to be fetched, oper-

ated on and possibly written. As can be seen from this description, the bus can become

extremely congested. With a Harvard architecture, the instruction is fetched in a single instruction

cycle (all 16 bits). While the program memory is being accessed, the data memory is on an inde-

pendent bus and can be read and written. These separated busses allow one instruction to exe-

cute, while the next instruction is fetched. A comparison of Harvard and von Neumann

architectures is shown in Figure 4-1.

Figure 4-1: Harvard vs. von Neumann Block Architectures

Long Word Instructions:

Long word instructions have a wider (more bits) instruction bus than the 8-bit data memory bus.

This is possible because the two buses are separate. This allows instructions to be sized differ-

ently than the 8-bit wide data word and allows a more efficient use of the program memory, since

the program memory width is optimized to the architectural requirements.

Single Word Instructions:

Single word instruction opcodes are 16-bits wide making it possible to have all but a few instruc-

tions be single word instructions. A 16-bit wide program memory access bus fetches a 16-bit

instruction in a single cycle. With single word instructions, the number of words of program mem-

ory locations equals the number of instructions for the device. This means that all locations are

valid instructions.

Typically in the von Neumann architecture, most instructions are multi-byte. In general, a device

with 4 Kbytes of program memory would allow approximately 2K of instructions. This 2:1 ratio is

generalized and dependent on the application code. Since each instruction may take multiple

bytes, there is no assurance that each location is a valid instruction.

Program

Memory

Data

Memory

Program

Memory

and

Data

CPU

CPU

8

8

16

Harvard

von Neumann