| 数据搜索系统,热门电子元器件搜索 |
|
AC206-DS03-R 数据表(PDF) 26 Page - Broadcom Corporation. |
|
|
|||||||||||||||||||||||||||||
AC206-DS03-R 数据表(HTML) 26 Page - Broadcom Corporation. |
|
26 / 70 page ![]() AC206 Preliminary Data Sheet 07/08/02 B roa dcom Page 14 Pin Descriptions Document AC206-DS05-405-R Table 6: Reverse Media Independent Interface Pins Pin Name Pin # Type Description RvMII_TXD3 (MII_RXD3) RvMII_TXD2 (MII_RXD2) RvMII_TXD1 (MII_RXD1) RvMII_TXD0 (MII_RXD0) 38 37 36 35 O MII Transmit Data. The MAC sources RvMII_TXD[3:0] synchronous with RvMII_TXCLK when RvMII_TXEN is asserted. RvMII_TXCLK (MII_TXCLK) 33 I,D,S MII Transmit Clock. Continuous (25 MHz/2.5 MHz) clock output used by MAC to synchronize RvMII_TXEN, RvMII_TXD[3:0], and RvMII_TXER. RvMII_TXEN (MII_RXDV) 28 O MII Transmit Enable. Indicates MAC has presented valid data on the RvMII_TXD[3:0]. RvMII_RXD3 (MII_TXD3) RvMII_RXD2 (MII_TXD2) RvMII_RXD1 (MII_TXD1) RvMII_RXD0 (MII_TXD0) 44 43 42 41 I,D MII Receive Data. The PHY sources RvMII_RXD[3:0] synchronous with RvMII_RXCLK when RvMII_RXDV is asserted. RvMII_RXCLK (MII_RXCLK) 31 I,D,S MII Transmit Clock. Continuous (25 MHz/2.5 MHz) clock output used by MAC to synchronize RvMII_RXDV, RvMII_RXD[3:0], and RvMII_RXER. RvMII_RXDV (MII_TXEN) 40 I,D MII Receive Data-Valid. PHY has presented valid recovered on the RvMII_RXD[3:0]. RvMII_CRS (MII_CRS) 29 I,D RvMII Carrier Sense. Active when carrier has been sensed. RvMII_RXER (MII_RXER) 34 I,D RvMII Receive Error. Indicates PHY has received invalid symbol data. RvMII_COL (MII_COL) 30 I,D RvMII Collision Detection. Active when collision is detected. Table 7: Seven-Wire (Serial Network Interface) Pins Pin Name Pin # Type Description SNI_TXD (MII_TXD0) 41 I,D Serial Transmit Data. The MAC sources SNI_TXD synchronous with SNI_TXCLK when SNI_TXEN is asserted. SNI_TXCLK (MII_TXCLK) 33 O Serial Transmit Clock. Continuous (10 MHz) clock output used by MAC to synchronize SNI_TXEN and SNI_TXD. SNI_TXEN (MII_TXEN) 40 I,D Serial Transmit Enable. Indicates MAC has presented valid data on the SNI_TXD. SNI_RXD (MII_RXD0) 35 O Serial Receive Data. The PHY sources SNI_RXD synchronous with SNI_RXCLK when SNI_CRS is asserted. SNI_RXCLK (MII_RXCLK) 31 O Serial Receive Clock. Continuous (10 MHz) clock output used by MAC to synchronize SNI_CRS and SNI_RXD. SNI_CRS (MII_CRS) 29 O Serial Carrier Sense. Active when carrier has been sensed. SNI_COL (MII_COL) 30 O Serial Collision Detection. Active when collision is detected. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |