AC206-DS02-R datasheet(27/70 Pages) BOARDCOM

27 / 70 page

Preliminary Data Sheet

AC206

07/08/02

B roa dcom

Document

AC206-DS05-405-R

Pin Descriptions

Page 15

Table 8: EEPROM Interface

Pin Name

Pin #

Type

Description

PROM_CS

127

PROM chip select. Connected to Chip Select pin of 93C46 serial

EEPROM

PROM_CLK (LED_D[6])

124

PROM Clock. Connected to CLK pin of 93C46 serial EEPROM

PROM_OUT (LED_D[5])

123

PROM Data Out. Connected to Data_In pin of 93C46 serial

EEPROM

PROM_IN (LED_D[7])

125

I,D

PROM Data In. Connected to Data_Out pin of 93C46 serial

EEPROM

Table 9: MDC/MDIO Interface

Pin Name

Pin #

Type

Description

MDC (PROM_CS)

127

I,U

Clock signal between the external device and PHY registers for

communication synchronization

MDIO

128

I/O,D

Data Input/Output. It is a bi-directional data interface used by the

external device to access only the internal PHY registers within

AC206. This pin has internal pull-down register.

Table 10: 100 Mbps Internal Repeater Bus

Pin Name

Pin #

Type

Description

M100COL_LOCAL*

I/O, U

100M Local Collision. Input when ChipID = 00. Active low to

indicate collision on all other ChipIds.

M100ACTO*

O, U

Output to ChipID=00 for ChipID

≠00 to signal local activity. This

signal is pure combinational logic and is not in sync with any clock

source. (Refer to next 3 signals).

M100ACTI_0*

(M100ACTO*)

I,U

Input for ChipID=00 from ChipID

≠00 M100ACTO* pins to indicate

activities. Open on all other ChipIDs.

M100ACTI_1*

I,U

Connected from ChipID=00 to ChipID=10 M100ACTO* to sense

activities. Open on all other ChipIDs.

M100ACTI_2*

I,U

Connected from ChipID=00 to ChipID=11 M100ACTO* to sense

activities. Open on all other ChipIDs.

M100COL_SYS*

I/O,U

ChipID=00 drives this pin the same as 100COLBP* to indicate

local collision.

M100CRS_SYS*

I/O,U

ChipID=00 drives this pin the same as 100CRSBP* to indicate

local activity.

MS100D4

MS100D3

MS100D2

MS100D1

MS100D0

I/O,D

Multiple/Stacked Data Group. Transmit and receive data in de-

scrambled 5B data groups for multiple devices. Data is sampled

at the rising edge of MS100D_CLK and driven out on falling edge

of MS100D_CLK.

MS100D_EN*

I/O,U

Multiple/Stacked Data Enable. Active-low when data is valid.

Signal is driven out on the falling edge of MS100D_CLK, and

sampled at the rising edge of MS100D_CLK.

MS100D_CLK

I/O, U,

Multiple/Stacked Data Clock. The bi-directional non-continuous

25 MHz recovered clock for synchronizing with MS100D[4:0], and

MS100D_EN*.

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