AC208-DS01-R datasheet(10/58 Pages) BOARDCOM

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AC208

Preliminary Data Sheet

07/08/02

B roa dcom

Page 2

Transceiver and Transmit Function

Document

AC208-DS04-405-R

TRANSCEIVER AND TRANSMIT FUNCTION

In 100BASE-TX mode, the Transceiver transmits MLT-3 signal to the cable via isolation transformer. MLT-3 data is a three

level signal data. This data is scrambled when transmitted to the media. The MLT-3 data is synchronous to the 25-MHz clock.

In 10BASE-T mode, Manchester code is generated by the 10BASE-T core logic, which synthesizes through the output

waveshaping driver. This helps reduce any EMI emission, which eliminates the need for an external filter.

MEDIA INDEPENDENT INTERFACE

The Media Independent Interface (MII) is for direct connection of an external device to the repeater. The transmit data on

the MII interface is 4-bit nibbles at 25/2.5 MHz rate. This MII interface is connected to the repeater via the MII TXD lines. The

external device asserts TX_EN during transmission, or forces an error in the encoded data using TX_ER.

SCRAMBLER

In 100BASE-TX mode, the internal 5-bit transmit data stream is scrambled as defined by the TP-PMD Stream Cipher

function in order to reduce radiated emissions on the twisted pair cable. The scrambler encodes a plain text NRZ bit stream

using a key stream periodic sequence of 2047 bits generated by the recursive linear function:

X [n] = X [n-11] + X [n-9] (modulo 2)

The scrambler reduces peak emissions by randomly spreading the signal energy over the transmit frequency range, thus

eliminating peaks at a single frequency. EMI emission can be further reduced by assigning a unique scrambled seed to each

port. When the BASE-T Control register 23.11 is set to 1 the data scrambling function is disabled, the 5-bit data stream is

clocked directly to the device’s PMA sublayer.

PARALLEL TO SERIAL AND NRZ—NRZI TO MLT-3 CONVERSION

The internal 5-bit NRZ data is clocked into transceiver’s shift register with a 25 MHz clock, and clocked out with a 125 MHz

clock to convert it into a serial bit stream. Both clocks are generated by an on-chip clock synthesizer, and they are in sync

to each other. The serialized data is further converted from NRZ to NRZI format, which produces a transition on every logic 1

and no transition on logic 0. To further reduce EMI emission, the NRZI data is converted to MLT-3 signal. The effect offers

a 3 dB to 6 dB reduction in EMI emissions over an un-converted NRZI signals, thus increases the output signals’ margin of

operating within the FCC Class B limit.

When there is a transition occurring in NRZI data, there is a corresponding transition for MLT-3 data. For NRZI data, it

changes the count up/down direction after every single transition. For MLT-3 data, it changes the count up/down direction

after every two transitions. The NRZI to MLT-3 data conversion is implemented without reference to the bit timing or clock

information. The conversion requires detecting transition of the incoming NRZI data and set up the count up/down direction

for the MLT-3 data. Asserting FX_SEL high bypasses this encoding.

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